2014-07-11 14:31:38 +01:00
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/*
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* Author: Thomas Ingleby <thomas.c.ingleby@intel.com>
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* Copyright (c) 2014 Intel Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <stdlib.h>
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#include <string.h>
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#include "common.h"
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2014-07-16 17:24:08 +01:00
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#include "intel_edison_fab_c.h"
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2014-07-11 14:31:38 +01:00
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2014-09-09 11:56:42 +01:00
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#define SYSFS_CLASS_GPIO "/sys/class/gpio"
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2014-07-21 13:59:32 +01:00
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#define SYSFS_PINMODE_PATH "/sys/kernel/debug/gpio_debug/gpio"
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#define MAX_SIZE 64
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#define MAX_MODE_SIZE 8
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typedef struct {
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int sysfs;
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int mode;
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} mraa_intel_edision_pindef_t;
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typedef struct {
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mraa_intel_edision_pindef_t gpio;
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mraa_intel_edision_pindef_t pwm;
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mraa_intel_edision_pindef_t i2c;
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mraa_intel_edision_pindef_t spi;
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mraa_intel_edision_pindef_t uart;
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} mraa_intel_edison_pinmodes_t;
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2014-07-21 14:17:35 +01:00
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static mraa_gpio_context tristate;
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2014-07-21 13:59:32 +01:00
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static mraa_intel_edison_pinmodes_t pinmodes[MRAA_INTEL_EDISON_PINCOUNT];
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static unsigned int outputen[] = {248,249,250,251,252,253,254,255,256,257,258,259,260,261,232,233,234,235,236,237};
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2014-07-28 17:51:28 +01:00
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static unsigned int pullup_map[] = {216,217,218,219,220,221,222,223,224,225,226,227,228,229,208,209,210,211,212,213};
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2014-10-07 19:20:03 +01:00
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static int miniboard = 0;
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2014-07-21 13:59:32 +01:00
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static mraa_result_t
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mraa_intel_edison_pinmode_change(int sysfs, int mode)
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{
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2014-07-21 17:43:38 +01:00
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if (mode < 0 ) {
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return MRAA_SUCCESS;
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}
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2014-07-21 13:59:32 +01:00
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char buffer[MAX_SIZE];
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snprintf(buffer, MAX_SIZE, SYSFS_PINMODE_PATH "%i/current_pinmux",sysfs);
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int modef = open(buffer, O_WRONLY);
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if (modef == -1) {
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2014-10-22 21:06:45 +01:00
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syslog(LOG_ERR, "edison: Failed to open SoC pinmode for opening");
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2014-07-21 13:59:32 +01:00
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return MRAA_ERROR_INVALID_RESOURCE;
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}
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char mode_buf[MAX_MODE_SIZE];
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int length = sprintf(mode_buf, "mode%u",mode);
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if (write(modef, mode_buf, length*sizeof(char)) == -1) {
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2014-10-03 22:50:18 +01:00
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close(modef);
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2014-07-21 13:59:32 +01:00
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return MRAA_ERROR_INVALID_RESOURCE;
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}
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close(modef);
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return MRAA_SUCCESS;
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}
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mraa_result_t
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mraa_intel_edison_gpio_dir_pre(mraa_gpio_context dev, gpio_dir_t dir)
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{
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2014-07-21 17:43:38 +01:00
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mraa_gpio_write(tristate, 0);
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2014-07-21 13:59:32 +01:00
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if (dev->phy_pin >= 0) {
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int pin = dev->phy_pin;
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mraa_gpio_context output_e;
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output_e = mraa_gpio_init_raw(outputen[pin]);
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if (mraa_gpio_dir(output_e, MRAA_GPIO_OUT) != MRAA_SUCCESS)
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return MRAA_ERROR_INVALID_RESOURCE;
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int output_val = 0;
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if (dir == MRAA_GPIO_OUT)
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output_val = 1;
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if (mraa_gpio_write(output_e, output_val) != MRAA_SUCCESS)
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return MRAA_ERROR_INVALID_RESOURCE;
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}
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return MRAA_SUCCESS;
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}
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2014-07-21 14:17:35 +01:00
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mraa_result_t
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mraa_intel_edison_gpio_dir_post(mraa_gpio_context dev, gpio_dir_t dir)
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{
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2014-07-21 17:43:38 +01:00
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mraa_gpio_write(tristate, 1);
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return MRAA_SUCCESS;
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2014-07-21 14:17:35 +01:00
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}
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2014-07-21 13:59:32 +01:00
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mraa_result_t
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mraa_intel_edison_gpio_init_post(mraa_gpio_context dev)
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{
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if (dev == NULL)
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return MRAA_ERROR_INVALID_RESOURCE;
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2014-10-07 19:20:03 +01:00
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int sysfs, mode;
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if (miniboard == 1) {
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sysfs = dev->pin;
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mode = 0;
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} else {
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sysfs = pinmodes[dev->phy_pin].gpio.sysfs;
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mode = pinmodes[dev->phy_pin].gpio.mode;
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}
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2014-07-21 13:59:32 +01:00
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mraa_result_t ret = mraa_intel_edison_pinmode_change(sysfs, mode);
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2014-07-28 14:56:01 +02:00
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return ret;
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2014-07-21 13:59:32 +01:00
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}
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2014-07-24 14:02:53 +01:00
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mraa_result_t
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mraa_intel_edison_i2c_init_pre(unsigned int bus)
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{
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2014-10-08 17:08:44 +01:00
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if (miniboard == 0) {
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if(bus != 6) {
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2014-10-22 21:06:45 +01:00
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syslog(LOG_ERR, "edison: You can't use that bus, switching to bus 6");
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2014-10-22 20:51:13 +01:00
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bus = 6;
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2014-10-08 17:08:44 +01:00
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}
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mraa_gpio_write(tristate, 0);
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mraa_gpio_context io18_gpio = mraa_gpio_init_raw(14);
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mraa_gpio_context io19_gpio = mraa_gpio_init_raw(165);
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mraa_gpio_dir(io18_gpio, MRAA_GPIO_IN);
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mraa_gpio_dir(io19_gpio, MRAA_GPIO_IN);
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mraa_gpio_close(io18_gpio);
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mraa_gpio_close(io19_gpio);
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mraa_gpio_context io18_enable = mraa_gpio_init_raw(236);
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mraa_gpio_context io19_enable = mraa_gpio_init_raw(237);
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mraa_gpio_dir(io18_enable, MRAA_GPIO_OUT);
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mraa_gpio_dir(io19_enable, MRAA_GPIO_OUT);
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mraa_gpio_write(io18_enable, 0);
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mraa_gpio_write(io19_enable, 0);
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mraa_gpio_close(io18_enable);
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mraa_gpio_close(io19_enable);
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mraa_gpio_context io18_pullup = mraa_gpio_init_raw(212);
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mraa_gpio_context io19_pullup = mraa_gpio_init_raw(213);
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mraa_gpio_dir(io18_pullup, MRAA_GPIO_IN);
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mraa_gpio_dir(io19_pullup, MRAA_GPIO_IN);
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mraa_gpio_close(io18_pullup);
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mraa_gpio_close(io19_pullup);
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mraa_intel_edison_pinmode_change(28, 1);
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mraa_intel_edison_pinmode_change(27, 1);
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mraa_gpio_write(tristate, 1);
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} else {
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if(bus != 6 && bus != 1) {
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2014-10-22 21:06:45 +01:00
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syslog(LOG_ERR, "edison: You can't use that bus, switching to bus 6");
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2014-10-22 20:51:13 +01:00
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bus = 6;
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2014-10-08 17:08:44 +01:00
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}
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int scl = plat->pins[plat->i2c_bus[bus].scl].gpio.pinmap;
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int sda = plat->pins[plat->i2c_bus[bus].sda].gpio.pinmap;
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mraa_intel_edison_pinmode_change(sda, 1);
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mraa_intel_edison_pinmode_change(scl, 1);
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2014-07-24 14:02:53 +01:00
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}
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return MRAA_SUCCESS;
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}
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2014-07-28 17:51:28 +01:00
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static mraa_result_t
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mraa_intel_edison_misc_spi()
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{
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mraa_gpio_write(tristate, 0);
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mraa_gpio_context io10_p1 = mraa_gpio_init_raw(263);
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mraa_gpio_context io10_p2 = mraa_gpio_init_raw(240);
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mraa_gpio_context io11_p1 = mraa_gpio_init_raw(262);
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mraa_gpio_context io11_p2 = mraa_gpio_init_raw(241);
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mraa_gpio_context io12_p1 = mraa_gpio_init_raw(242);
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mraa_gpio_context io13_p1 = mraa_gpio_init_raw(243);
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mraa_gpio_dir(io10_p1, MRAA_GPIO_OUT);
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mraa_gpio_dir(io10_p2, MRAA_GPIO_OUT);
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mraa_gpio_dir(io11_p1, MRAA_GPIO_OUT);
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mraa_gpio_dir(io11_p2, MRAA_GPIO_OUT);
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mraa_gpio_dir(io12_p1, MRAA_GPIO_OUT);
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mraa_gpio_dir(io13_p1, MRAA_GPIO_OUT);
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mraa_gpio_write(io10_p1, 1);
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mraa_gpio_write(io10_p2, 0);
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mraa_gpio_write(io11_p1, 1);
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mraa_gpio_write(io11_p2, 0);
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mraa_gpio_write(io12_p1, 0);
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mraa_gpio_write(io13_p1, 0);
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mraa_gpio_close(io10_p1);
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mraa_gpio_close(io10_p2);
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mraa_gpio_close(io11_p1);
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mraa_gpio_close(io11_p2);
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mraa_gpio_close(io12_p1);
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mraa_gpio_close(io13_p1);
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mraa_intel_edison_pinmode_change(111, 1);
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mraa_intel_edison_pinmode_change(115, 1);
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mraa_intel_edison_pinmode_change(114, 1);
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mraa_intel_edison_pinmode_change(109, 1);
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mraa_gpio_write(tristate, 1);
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return MRAA_SUCCESS;
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}
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mraa_result_t
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mraa_intel_edison_aio_get_fp(mraa_aio_context dev)
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{
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char file_path[64]= "";
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snprintf(file_path, 64, "/sys/bus/iio/devices/iio:device1/in_voltage%d_raw",
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2014-09-25 14:31:04 +01:00
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dev->channel );
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2014-07-28 17:51:28 +01:00
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dev->adc_in_fp = open(file_path, O_RDONLY);
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if (dev->adc_in_fp == -1) {
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2014-10-22 21:06:45 +01:00
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syslog(LOG_ERR, "edison: Failed to open Analog input raw file %s for "
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2014-09-25 14:31:04 +01:00
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"reading!", file_path);
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return MRAA_ERROR_INVALID_RESOURCE;
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2014-07-28 17:51:28 +01:00
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}
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return MRAA_SUCCESS;
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}
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mraa_result_t
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mraa_intel_edison_aio_init_pre(unsigned int aio)
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{
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if (aio > plat->aio_count) {
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2014-10-22 21:06:45 +01:00
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syslog(LOG_ERR, "edison: Invalid analog input channel");
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2014-07-28 17:51:28 +01:00
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return MRAA_ERROR_INVALID_RESOURCE;
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}
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int pin = 14 + aio;
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mraa_gpio_context output_e;
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output_e = mraa_gpio_init_raw(outputen[pin]);
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if (mraa_gpio_dir(output_e, MRAA_GPIO_OUT) != MRAA_SUCCESS)
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return MRAA_ERROR_INVALID_RESOURCE;
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if (mraa_gpio_write(output_e, 0) != MRAA_SUCCESS)
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return MRAA_ERROR_INVALID_RESOURCE;
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mraa_gpio_close(output_e);
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mraa_gpio_context pullup_pin;
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pullup_pin = mraa_gpio_init_raw(pullup_map[pin]);
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if (mraa_gpio_dir(pullup_pin, MRAA_GPIO_IN) != MRAA_SUCCESS)
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return MRAA_ERROR_INVALID_RESOURCE;
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mraa_gpio_close(pullup_pin);
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return MRAA_SUCCESS;
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}
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mraa_result_t
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mraa_intel_edison_aio_init_post(mraa_aio_context dev)
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{
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mraa_gpio_write(tristate, 1);
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return MRAA_SUCCESS;
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}
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2014-07-29 15:31:42 +01:00
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mraa_result_t
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mraa_intel_edison_pwm_init_pre(int pin)
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{
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2014-10-07 19:20:03 +01:00
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if (miniboard == 1) {
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|
|
return mraa_intel_edison_pinmode_change(plat->pins[pin].gpio.pinmap, 1);
|
|
|
|
|
}
|
2014-07-29 15:31:42 +01:00
|
|
|
if (pin < 0 || pin > 19)
|
|
|
|
|
return MRAA_ERROR_INVALID_RESOURCE;
|
|
|
|
|
|
|
|
|
|
if (!plat->pins[pin].capabilites.pwm)
|
|
|
|
|
return MRAA_ERROR_INVALID_RESOURCE;
|
|
|
|
|
|
|
|
|
|
mraa_gpio_context output_e;
|
|
|
|
|
output_e = mraa_gpio_init_raw(outputen[pin]);
|
|
|
|
|
if (mraa_gpio_dir(output_e, MRAA_GPIO_OUT) != MRAA_SUCCESS)
|
|
|
|
|
return MRAA_ERROR_INVALID_RESOURCE;
|
|
|
|
|
if (mraa_gpio_write(output_e, 1) != MRAA_SUCCESS)
|
|
|
|
|
return MRAA_ERROR_INVALID_RESOURCE;
|
|
|
|
|
mraa_gpio_close(output_e);
|
|
|
|
|
|
|
|
|
|
mraa_gpio_context pullup_pin;
|
|
|
|
|
pullup_pin = mraa_gpio_init_raw(pullup_map[pin]);
|
|
|
|
|
if (mraa_gpio_dir(pullup_pin, MRAA_GPIO_IN) != MRAA_SUCCESS)
|
|
|
|
|
return MRAA_ERROR_INVALID_RESOURCE;
|
|
|
|
|
mraa_gpio_close(pullup_pin);
|
|
|
|
|
mraa_intel_edison_pinmode_change(plat->pins[pin].gpio.pinmap, 1);
|
|
|
|
|
|
|
|
|
|
return MRAA_SUCCESS;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mraa_result_t
|
|
|
|
|
mraa_intel_edison_pwm_init_post(mraa_pwm_context pwm)
|
|
|
|
|
{
|
|
|
|
|
mraa_gpio_write(tristate, 1);
|
|
|
|
|
return MRAA_SUCCESS;
|
|
|
|
|
}
|
|
|
|
|
|
2014-07-31 14:53:03 +01:00
|
|
|
mraa_result_t
|
|
|
|
|
mraa_intel_edison_spi_init_pre(int bus)
|
|
|
|
|
{
|
2014-10-08 17:23:45 +01:00
|
|
|
if (miniboard == 1) {
|
|
|
|
|
mraa_intel_edison_pinmode_change(111, 1);
|
|
|
|
|
mraa_intel_edison_pinmode_change(115, 1);
|
|
|
|
|
mraa_intel_edison_pinmode_change(114, 1);
|
|
|
|
|
mraa_intel_edison_pinmode_change(109, 1);
|
|
|
|
|
return MRAA_SUCCESS;
|
|
|
|
|
}
|
2014-07-31 14:53:03 +01:00
|
|
|
mraa_gpio_write(tristate, 0);
|
|
|
|
|
|
|
|
|
|
mraa_gpio_context io10_out = mraa_gpio_init_raw(258);
|
|
|
|
|
mraa_gpio_context io11_out = mraa_gpio_init_raw(259);
|
|
|
|
|
mraa_gpio_context io12_out = mraa_gpio_init_raw(260);
|
|
|
|
|
mraa_gpio_context io13_out = mraa_gpio_init_raw(261);
|
|
|
|
|
mraa_gpio_dir(io10_out, MRAA_GPIO_OUT);
|
|
|
|
|
mraa_gpio_dir(io11_out, MRAA_GPIO_OUT);
|
|
|
|
|
mraa_gpio_dir(io12_out, MRAA_GPIO_OUT);
|
|
|
|
|
mraa_gpio_dir(io13_out, MRAA_GPIO_OUT);
|
|
|
|
|
|
|
|
|
|
mraa_gpio_write(io10_out, 1);
|
|
|
|
|
mraa_gpio_write(io11_out, 1);
|
|
|
|
|
mraa_gpio_write(io12_out, 0);
|
|
|
|
|
mraa_gpio_write(io13_out, 1);
|
|
|
|
|
|
|
|
|
|
mraa_gpio_close(io10_out);
|
|
|
|
|
mraa_gpio_close(io11_out);
|
|
|
|
|
mraa_gpio_close(io12_out);
|
|
|
|
|
mraa_gpio_close(io13_out);
|
|
|
|
|
|
|
|
|
|
mraa_gpio_context io10_pull = mraa_gpio_init_raw(226);
|
|
|
|
|
mraa_gpio_context io11_pull = mraa_gpio_init_raw(227);
|
|
|
|
|
mraa_gpio_context io12_pull = mraa_gpio_init_raw(228);
|
|
|
|
|
mraa_gpio_context io13_pull = mraa_gpio_init_raw(229);
|
|
|
|
|
|
|
|
|
|
mraa_gpio_dir(io10_pull, MRAA_GPIO_IN);
|
|
|
|
|
mraa_gpio_dir(io11_pull, MRAA_GPIO_IN);
|
|
|
|
|
mraa_gpio_dir(io12_pull, MRAA_GPIO_IN);
|
|
|
|
|
mraa_gpio_dir(io13_pull, MRAA_GPIO_IN);
|
|
|
|
|
|
|
|
|
|
mraa_gpio_close(io10_pull);
|
|
|
|
|
mraa_gpio_close(io11_pull);
|
|
|
|
|
mraa_gpio_close(io12_pull);
|
|
|
|
|
mraa_gpio_close(io13_pull);
|
|
|
|
|
|
|
|
|
|
return MRAA_SUCCESS;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mraa_result_t
|
|
|
|
|
mraa_intel_edison_spi_init_post(mraa_spi_context spi)
|
|
|
|
|
{
|
|
|
|
|
mraa_gpio_write(tristate, 1);
|
|
|
|
|
return MRAA_SUCCESS;
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-09 11:56:42 +01:00
|
|
|
mraa_result_t
|
|
|
|
|
mraa_intel_edison_gpio_mode_replace(mraa_gpio_context dev, gpio_mode_t mode)
|
|
|
|
|
{
|
|
|
|
|
if (dev->value_fp != -1) {
|
|
|
|
|
close(dev->value_fp);
|
|
|
|
|
dev->value_fp = -1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mraa_gpio_context pullup_e;
|
|
|
|
|
pullup_e = mraa_gpio_init_raw(pullup_map[dev->phy_pin]);
|
|
|
|
|
mraa_result_t sta = mraa_gpio_dir(pullup_e, MRAA_GPIO_IN);
|
|
|
|
|
if(sta != MRAA_SUCCESS) {
|
2014-10-22 21:06:45 +01:00
|
|
|
syslog(LOG_ERR, "edison: Failed to set gpio mode-pullup");
|
2014-09-25 14:31:04 +01:00
|
|
|
return MRAA_ERROR_INVALID_RESOURCE;
|
2014-09-09 11:56:42 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int value = -1;
|
|
|
|
|
switch(mode) {
|
|
|
|
|
case MRAA_GPIO_STRONG:
|
|
|
|
|
break;
|
|
|
|
|
case MRAA_GPIO_PULLUP:
|
|
|
|
|
value = 1;
|
|
|
|
|
break;
|
|
|
|
|
case MRAA_GPIO_PULLDOWN:
|
|
|
|
|
value = 0;
|
|
|
|
|
break;
|
|
|
|
|
case MRAA_GPIO_HIZ:
|
|
|
|
|
return MRAA_SUCCESS;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
return MRAA_ERROR_FEATURE_NOT_IMPLEMENTED;
|
|
|
|
|
}
|
|
|
|
|
if (value != -1) {
|
|
|
|
|
sta = mraa_gpio_dir(pullup_e, MRAA_GPIO_OUT);
|
|
|
|
|
sta = mraa_gpio_write(pullup_e, value);
|
|
|
|
|
if (sta != MRAA_SUCCESS) {
|
2014-10-22 21:06:45 +01:00
|
|
|
syslog(LOG_ERR, "edison: Error setting pullup");
|
2014-09-09 11:56:42 +01:00
|
|
|
return sta;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return MRAA_SUCCESS;
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-08 18:02:53 +01:00
|
|
|
mraa_result_t
|
|
|
|
|
mraa_intel_edsion_mb_gpio_mode(mraa_gpio_context dev, gpio_mode_t mode)
|
|
|
|
|
{
|
|
|
|
|
if (dev->value_fp != -1) {
|
|
|
|
|
close(dev->value_fp);
|
|
|
|
|
dev->value_fp = -1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
char filepath[MAX_SIZE];
|
|
|
|
|
snprintf(filepath, MAX_SIZE,
|
|
|
|
|
SYSFS_PINMODE_PATH "%d/current_pullmode", dev->pin);
|
|
|
|
|
|
|
|
|
|
int drive = open(filepath, O_WRONLY);
|
|
|
|
|
if (drive == -1) {
|
2014-10-22 21:06:45 +01:00
|
|
|
syslog(LOG_ERR, "edison: Failed to open drive for writing");
|
2014-10-08 18:02:53 +01:00
|
|
|
return MRAA_ERROR_INVALID_RESOURCE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
char bu[MAX_SIZE];
|
|
|
|
|
int length;
|
|
|
|
|
switch(mode) {
|
|
|
|
|
case MRAA_GPIO_STRONG:
|
|
|
|
|
close(drive);
|
|
|
|
|
return MRAA_SUCCESS;
|
|
|
|
|
case MRAA_GPIO_PULLUP:
|
|
|
|
|
length = snprintf(bu, sizeof(bu), "pullup");
|
|
|
|
|
break;
|
|
|
|
|
case MRAA_GPIO_PULLDOWN:
|
|
|
|
|
length = snprintf(bu, sizeof(bu), "pulldown");
|
|
|
|
|
break;
|
|
|
|
|
case MRAA_GPIO_HIZ:
|
|
|
|
|
length = snprintf(bu, sizeof(bu), "nopull");
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
close(drive);
|
|
|
|
|
return MRAA_ERROR_FEATURE_NOT_IMPLEMENTED;
|
|
|
|
|
}
|
|
|
|
|
if (write(drive, bu, length*sizeof(char)) == -1) {
|
2014-10-22 21:06:45 +01:00
|
|
|
syslog(LOG_ERR, "edison: Failed to write to drive mode");
|
2014-10-08 18:02:53 +01:00
|
|
|
close(drive);
|
|
|
|
|
return MRAA_ERROR_INVALID_RESOURCE;
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
close(drive);
|
|
|
|
|
return MRAA_SUCCESS;
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-19 16:25:47 +01:00
|
|
|
mraa_result_t
|
2014-10-20 19:13:43 +01:00
|
|
|
mraa_intel_edison_uart_init_pre(int index)
|
2014-10-19 16:25:47 +01:00
|
|
|
{
|
2014-10-20 19:13:43 +01:00
|
|
|
if (miniboard == 0) {
|
|
|
|
|
mraa_gpio_write(tristate, 0);
|
|
|
|
|
mraa_gpio_context io0_output = mraa_gpio_init_raw(248);
|
|
|
|
|
mraa_gpio_context io0_pullup = mraa_gpio_init_raw(216);
|
|
|
|
|
mraa_gpio_context io1_output = mraa_gpio_init_raw(249);
|
|
|
|
|
mraa_gpio_context io1_pullup = mraa_gpio_init_raw(217);
|
|
|
|
|
mraa_gpio_dir(io0_output, MRAA_GPIO_OUT);
|
|
|
|
|
mraa_gpio_dir(io0_pullup, MRAA_GPIO_OUT);
|
|
|
|
|
mraa_gpio_dir(io1_output, MRAA_GPIO_OUT);
|
|
|
|
|
mraa_gpio_dir(io1_pullup, MRAA_GPIO_IN);
|
|
|
|
|
|
|
|
|
|
mraa_gpio_write(io0_output, 0);
|
|
|
|
|
mraa_gpio_write(io0_pullup, 0);
|
|
|
|
|
mraa_gpio_write(io1_output, 1);
|
|
|
|
|
|
|
|
|
|
mraa_gpio_close(io0_output);
|
|
|
|
|
mraa_gpio_close(io0_pullup);
|
|
|
|
|
mraa_gpio_close(io1_output);
|
|
|
|
|
mraa_gpio_close(io1_pullup);
|
|
|
|
|
}
|
2014-10-19 16:25:47 +01:00
|
|
|
mraa_result_t ret;
|
|
|
|
|
ret = mraa_intel_edison_pinmode_change(130,1); //IO0 RX
|
|
|
|
|
ret = mraa_intel_edison_pinmode_change(131,1); //IO1 TX
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-20 19:13:43 +01:00
|
|
|
mraa_result_t
|
|
|
|
|
mraa_intel_edison_uart_init_post(mraa_uart_context uart)
|
|
|
|
|
{
|
|
|
|
|
return mraa_gpio_write(tristate, 1);
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-07 19:20:03 +01:00
|
|
|
mraa_result_t
|
|
|
|
|
mraa_intel_edsion_miniboard(mraa_board_t* b)
|
|
|
|
|
{
|
|
|
|
|
miniboard = 1;
|
|
|
|
|
b->phy_pin_count = 56;
|
|
|
|
|
b->gpio_count = 56; // A bit of a hack I suppose
|
|
|
|
|
b->aio_count = 0;
|
2014-10-30 12:03:24 +00:00
|
|
|
b->pwm_default_period = 5000;
|
|
|
|
|
b->pwm_max_period = 218453;
|
|
|
|
|
b->pwm_min_period = 1;
|
|
|
|
|
|
2014-10-07 19:20:03 +01:00
|
|
|
|
|
|
|
|
b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t)*56);
|
|
|
|
|
|
|
|
|
|
advance_func->gpio_init_post = &mraa_intel_edison_gpio_init_post;
|
2014-10-08 15:24:04 +01:00
|
|
|
advance_func->pwm_init_pre = &mraa_intel_edison_pwm_init_pre;
|
2014-10-08 17:08:44 +01:00
|
|
|
advance_func->i2c_init_pre = &mraa_intel_edison_i2c_init_pre;
|
2014-10-08 17:23:45 +01:00
|
|
|
advance_func->spi_init_pre = &mraa_intel_edison_spi_init_pre;
|
2014-10-08 18:02:53 +01:00
|
|
|
advance_func->gpio_mode_replace = &mraa_intel_edsion_mb_gpio_mode;
|
2014-10-19 16:25:47 +01:00
|
|
|
advance_func->uart_init_post = &mraa_intel_edison_uart_init_post;
|
2014-10-07 19:20:03 +01:00
|
|
|
|
|
|
|
|
int pos = 0;
|
|
|
|
|
strncpy(b->pins[pos].name, "J17-1", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 182;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
b->pins[pos].pwm.pinmap = 2;
|
|
|
|
|
b->pins[pos].pwm.parent_id = 0;
|
|
|
|
|
b->pins[pos].pwm.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J17-2", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J17-3", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J17-4", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J17-5", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 135;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J17-6", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J17-7", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 27;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
b->pins[pos].i2c.pinmap = 1;
|
|
|
|
|
b->pins[pos].i2c.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J17-8", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 20;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
b->pins[pos].i2c.pinmap = 1;
|
|
|
|
|
b->pins[pos].i2c.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J17-9", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 28;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
b->pins[pos].i2c.pinmap = 1;
|
|
|
|
|
b->pins[pos].i2c.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J17-10", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 111;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
b->pins[pos].spi.pinmap = 5;
|
|
|
|
|
b->pins[pos].spi.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J17-11", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 109;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
b->pins[pos].spi.pinmap = 5;
|
|
|
|
|
b->pins[pos].spi.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J17-12", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 115;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
b->pins[pos].spi.pinmap = 5;
|
|
|
|
|
b->pins[pos].spi.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J17-13", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J17-14", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 128;
|
|
|
|
|
b->pins[pos].gpio.parent_id = 0;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J18-1", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 13;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
b->pins[pos].pwm.pinmap = 1;
|
|
|
|
|
b->pins[pos].pwm.parent_id = 0;
|
|
|
|
|
b->pins[pos].pwm.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J18-2", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 165;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J18-3", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J18-4", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J18-5", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J18-6", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 19;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
b->pins[pos].i2c.pinmap = 1;
|
|
|
|
|
b->pins[pos].i2c.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J18-7", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 12;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
b->pins[pos].pwm.pinmap = 0;
|
|
|
|
|
b->pins[pos].pwm.parent_id = 0;
|
|
|
|
|
b->pins[pos].pwm.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J18-8", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
|
2014-11-17 16:05:26 +00:00
|
|
|
b->pins[pos].gpio.pinmap = 183;
|
2014-10-07 19:20:03 +01:00
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
b->pins[pos].pwm.pinmap = 3;
|
|
|
|
|
b->pins[pos].pwm.parent_id = 0;
|
|
|
|
|
b->pins[pos].pwm.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J18-9", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J18-10", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 110;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
b->pins[pos].spi.pinmap = 5;
|
|
|
|
|
b->pins[pos].spi.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J18-11", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 114;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
b->pins[pos].spi.pinmap = 5;
|
|
|
|
|
b->pins[pos].spi.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J18-12", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 129;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J18-13", 8);
|
2014-10-20 19:13:43 +01:00
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,1};
|
2014-10-07 19:20:03 +01:00
|
|
|
b->pins[pos].gpio.pinmap = 130;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
2014-10-20 19:13:43 +01:00
|
|
|
b->pins[pos].uart.pinmap = 0;
|
|
|
|
|
b->pins[pos].uart.parent_id = 0;
|
|
|
|
|
b->pins[pos].uart.mux_total = 0;
|
|
|
|
|
|
2014-10-07 19:20:03 +01:00
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J18-14", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J19-1", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J19-2", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J19-3", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J19-4", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 44;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J19-5", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 46;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J19-6", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 48;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J19-7", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J19-8", 8);
|
2014-10-20 19:13:43 +01:00
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,1};
|
2014-10-07 19:20:03 +01:00
|
|
|
b->pins[pos].gpio.pinmap = 131;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
2014-10-20 19:13:43 +01:00
|
|
|
b->pins[pos].uart.pinmap = 0;
|
|
|
|
|
b->pins[pos].uart.parent_id = 0;
|
|
|
|
|
b->pins[pos].uart.mux_total = 0;
|
2014-10-07 19:20:03 +01:00
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J19-9", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 14;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J19-10", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 40;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J19-11", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 43;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J19-12", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 77;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J19-13", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 82;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J19-14", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 83;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[pos].name, "J20-1", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J20-2", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J20-3", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J20-4", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 45;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J20-5", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 47;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J20-6", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 49;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J20-7", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 15;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J20-8", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 84;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J20-9", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 42;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J20-10", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 41;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J20-11", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 78;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J20-12", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 79;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J20-13", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 80;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
strncpy(b->pins[pos].name, "J20-14", 8);
|
|
|
|
|
b->pins[pos].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
|
|
|
|
|
b->pins[pos].gpio.pinmap = 81;
|
|
|
|
|
b->pins[pos].gpio.mux_total = 0;
|
|
|
|
|
pos++;
|
|
|
|
|
|
2014-10-08 17:08:44 +01:00
|
|
|
//BUS DEFINITIONS
|
|
|
|
|
b->i2c_bus_count = 9;
|
|
|
|
|
b->def_i2c_bus = 6;
|
|
|
|
|
int ici;
|
|
|
|
|
for (ici = 0; ici < 9; ici++) {
|
|
|
|
|
b->i2c_bus[ici].bus_id = -1;
|
|
|
|
|
}
|
|
|
|
|
b->i2c_bus[1].bus_id = 1;
|
|
|
|
|
b->i2c_bus[1].sda = 7;
|
|
|
|
|
b->i2c_bus[1].scl = 19;
|
|
|
|
|
|
|
|
|
|
b->i2c_bus[6].bus_id = 6;
|
|
|
|
|
b->i2c_bus[6].sda = 8;
|
|
|
|
|
b->i2c_bus[6].scl = 6;
|
|
|
|
|
|
|
|
|
|
b->spi_bus_count = 1;
|
|
|
|
|
b->def_spi_bus = 0;
|
|
|
|
|
b->spi_bus[0].bus_id = 5;
|
|
|
|
|
b->spi_bus[0].slave_s = 1;
|
|
|
|
|
b->spi_bus[0].cs = 23;
|
|
|
|
|
b->spi_bus[0].mosi = 11;
|
|
|
|
|
b->spi_bus[0].miso = 24;
|
|
|
|
|
b->spi_bus[0].sclk = 10;
|
|
|
|
|
|
2014-10-20 19:13:43 +01:00
|
|
|
b->uart_dev_count = 1;
|
|
|
|
|
b->def_uart_dev = 0;
|
|
|
|
|
b->uart_dev[0].rx = 26;
|
|
|
|
|
b->uart_dev[0].tx = 35;
|
|
|
|
|
|
2014-10-07 19:20:03 +01:00
|
|
|
return MRAA_SUCCESS;
|
|
|
|
|
}
|
2014-09-09 11:56:42 +01:00
|
|
|
|
2014-07-11 14:31:38 +01:00
|
|
|
mraa_board_t*
|
2014-07-16 17:24:08 +01:00
|
|
|
mraa_intel_edison_fab_c()
|
2014-07-11 14:31:38 +01:00
|
|
|
{
|
|
|
|
|
mraa_board_t* b = (mraa_board_t*) malloc(sizeof(mraa_board_t));
|
|
|
|
|
if (b == NULL)
|
|
|
|
|
return NULL;
|
|
|
|
|
|
2014-10-07 19:20:03 +01:00
|
|
|
// This seciton will also check if the arduino board is there
|
|
|
|
|
tristate = mraa_gpio_init_raw(214);
|
|
|
|
|
if (tristate == NULL) {
|
2014-10-22 21:06:45 +01:00
|
|
|
syslog(LOG_INFO, "edison: Failed to initialise Arduino board TriState,\
|
2014-10-07 19:20:03 +01:00
|
|
|
assuming Intel Edison Miniboard\n");
|
|
|
|
|
if (mraa_intel_edsion_miniboard(b) != MRAA_SUCCESS) {
|
|
|
|
|
free(b);
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
return b;
|
|
|
|
|
}
|
|
|
|
|
// Now Assuming the edison is attached to the Arduino board.
|
2014-07-11 14:31:38 +01:00
|
|
|
b->phy_pin_count = 20;
|
|
|
|
|
b->gpio_count = 14;
|
|
|
|
|
b->aio_count = 6;
|
|
|
|
|
|
2014-07-21 13:59:32 +01:00
|
|
|
advance_func->gpio_dir_pre = &mraa_intel_edison_gpio_dir_pre;
|
|
|
|
|
advance_func->gpio_init_post = &mraa_intel_edison_gpio_init_post;
|
2014-07-21 14:17:35 +01:00
|
|
|
advance_func->gpio_dir_post = &mraa_intel_edison_gpio_dir_post;
|
2014-07-24 14:02:53 +01:00
|
|
|
advance_func->i2c_init_pre = &mraa_intel_edison_i2c_init_pre;
|
2014-07-28 17:51:28 +01:00
|
|
|
advance_func->aio_get_valid_fp = &mraa_intel_edison_aio_get_fp;
|
|
|
|
|
advance_func->aio_init_pre = &mraa_intel_edison_aio_init_pre;
|
|
|
|
|
advance_func->aio_init_post = &mraa_intel_edison_aio_init_post;
|
2014-07-29 15:31:42 +01:00
|
|
|
advance_func->pwm_init_pre = &mraa_intel_edison_pwm_init_pre;
|
|
|
|
|
advance_func->pwm_init_post = &mraa_intel_edison_pwm_init_post;
|
2014-07-31 14:53:03 +01:00
|
|
|
advance_func->spi_init_pre = &mraa_intel_edison_spi_init_pre;
|
|
|
|
|
advance_func->spi_init_post = &mraa_intel_edison_spi_init_post;
|
2014-09-09 11:56:42 +01:00
|
|
|
advance_func->gpio_mode_replace = &mraa_intel_edison_gpio_mode_replace;
|
2014-10-20 19:13:43 +01:00
|
|
|
advance_func->uart_init_pre = &mraa_intel_edison_uart_init_pre;
|
2014-10-19 16:25:47 +01:00
|
|
|
advance_func->uart_init_post = &mraa_intel_edison_uart_init_post;
|
2014-07-21 13:59:32 +01:00
|
|
|
|
2014-07-11 14:31:38 +01:00
|
|
|
b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t)*MRAA_INTEL_EDISON_PINCOUNT);
|
|
|
|
|
|
2014-07-21 14:17:35 +01:00
|
|
|
mraa_gpio_dir(tristate, MRAA_GPIO_OUT);
|
2014-07-28 17:51:28 +01:00
|
|
|
mraa_intel_edison_misc_spi();
|
2014-07-21 14:17:35 +01:00
|
|
|
|
2014-09-10 16:31:49 +01:00
|
|
|
b->adc_raw = 12;
|
|
|
|
|
b->adc_supported = 10;
|
2014-10-30 12:03:24 +00:00
|
|
|
b->pwm_default_period = 5000;
|
|
|
|
|
b->pwm_max_period = 218453;
|
|
|
|
|
b->pwm_min_period = 1;
|
2014-09-10 16:31:49 +01:00
|
|
|
|
2014-07-21 17:43:38 +01:00
|
|
|
strncpy(b->pins[0].name, "IO0", 8);
|
2014-10-19 16:25:47 +01:00
|
|
|
b->pins[0].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,1};
|
2014-07-21 17:43:38 +01:00
|
|
|
b->pins[0].gpio.pinmap = 130;
|
|
|
|
|
b->pins[0].gpio.parent_id = 0;
|
|
|
|
|
b->pins[0].gpio.mux_total = 0;
|
2014-10-19 16:25:47 +01:00
|
|
|
b->pins[0].uart.pinmap = 0;
|
|
|
|
|
b->pins[0].uart.parent_id = 0;
|
|
|
|
|
b->pins[0].uart.mux_total = 0;
|
2014-07-21 17:43:38 +01:00
|
|
|
|
|
|
|
|
strncpy(b->pins[1].name, "IO1", 8);
|
2014-10-19 16:25:47 +01:00
|
|
|
b->pins[1].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,1};
|
2014-07-21 17:43:38 +01:00
|
|
|
b->pins[1].gpio.pinmap = 131;
|
|
|
|
|
b->pins[1].gpio.parent_id = 0;
|
|
|
|
|
b->pins[1].gpio.mux_total = 0;
|
2014-10-19 16:25:47 +01:00
|
|
|
b->pins[1].uart.pinmap = 0;
|
|
|
|
|
b->pins[1].uart.parent_id = 0;
|
2014-10-20 19:13:43 +01:00
|
|
|
b->pins[1].uart.mux_total = 0;
|
2014-07-21 17:43:38 +01:00
|
|
|
|
|
|
|
|
strncpy(b->pins[2].name, "IO2", 8);
|
|
|
|
|
b->pins[2].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
|
|
|
|
|
b->pins[2].gpio.pinmap = 128;
|
|
|
|
|
b->pins[2].gpio.parent_id = 0;
|
|
|
|
|
b->pins[2].gpio.mux_total = 0;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[3].name, "IO3", 8);
|
2014-07-29 15:31:42 +01:00
|
|
|
b->pins[3].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
|
2014-07-21 17:43:38 +01:00
|
|
|
b->pins[3].gpio.pinmap = 12;
|
|
|
|
|
b->pins[3].gpio.parent_id = 0;
|
|
|
|
|
b->pins[3].gpio.mux_total = 0;
|
2014-07-29 15:31:42 +01:00
|
|
|
b->pins[3].pwm.pinmap = 0;
|
|
|
|
|
b->pins[3].pwm.parent_id = 0;
|
|
|
|
|
b->pins[3].pwm.mux_total = 0;
|
2014-07-21 14:17:35 +01:00
|
|
|
|
2014-07-21 13:59:32 +01:00
|
|
|
strncpy(b->pins[4].name, "IO4", 8);
|
|
|
|
|
b->pins[4].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
|
|
|
|
|
b->pins[4].gpio.pinmap = 129;
|
|
|
|
|
b->pins[4].gpio.parent_id = 0;
|
|
|
|
|
b->pins[4].gpio.mux_total = 0;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[5].name, "IO5", 8);
|
2014-07-29 15:31:42 +01:00
|
|
|
b->pins[5].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
|
2014-07-21 13:59:32 +01:00
|
|
|
b->pins[5].gpio.pinmap = 13;
|
|
|
|
|
b->pins[5].gpio.parent_id = 0;
|
|
|
|
|
b->pins[5].gpio.mux_total = 0;
|
2014-07-29 15:31:42 +01:00
|
|
|
b->pins[5].pwm.pinmap = 1;
|
|
|
|
|
b->pins[5].pwm.parent_id = 0;
|
|
|
|
|
b->pins[5].pwm.mux_total = 0;
|
2014-07-21 13:59:32 +01:00
|
|
|
|
2014-07-21 17:43:38 +01:00
|
|
|
strncpy(b->pins[6].name, "IO6", 8);
|
2014-07-29 15:31:42 +01:00
|
|
|
b->pins[6].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
|
2014-07-21 17:43:38 +01:00
|
|
|
b->pins[6].gpio.pinmap = 182;
|
|
|
|
|
b->pins[6].gpio.parent_id = 0;
|
|
|
|
|
b->pins[6].gpio.mux_total = 0;
|
2014-07-29 15:31:42 +01:00
|
|
|
b->pins[6].pwm.pinmap = 2;
|
|
|
|
|
b->pins[6].pwm.parent_id = 0;
|
|
|
|
|
b->pins[6].pwm.mux_total = 0;
|
2014-07-21 17:43:38 +01:00
|
|
|
|
|
|
|
|
strncpy(b->pins[7].name, "IO7", 8);
|
|
|
|
|
b->pins[7].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
|
|
|
|
|
b->pins[7].gpio.pinmap = 48;
|
|
|
|
|
b->pins[7].gpio.parent_id = 0;
|
|
|
|
|
b->pins[7].gpio.mux_total = 0;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[8].name, "IO8", 8);
|
|
|
|
|
b->pins[8].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
|
|
|
|
|
b->pins[8].gpio.pinmap = 49;
|
|
|
|
|
b->pins[8].gpio.parent_id = 0;
|
|
|
|
|
b->pins[8].gpio.mux_total = 0;
|
|
|
|
|
|
|
|
|
|
strncpy(b->pins[9].name, "IO9", 8);
|
2014-07-29 15:31:42 +01:00
|
|
|
b->pins[9].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
|
2014-07-21 17:43:38 +01:00
|
|
|
b->pins[9].gpio.pinmap = 183;
|
|
|
|
|
b->pins[9].gpio.parent_id = 0;
|
|
|
|
|
b->pins[9].gpio.mux_total = 0;
|
2014-07-29 15:31:42 +01:00
|
|
|
b->pins[9].pwm.pinmap = 3;
|
|
|
|
|
b->pins[9].pwm.parent_id = 0;
|
|
|
|
|
b->pins[9].pwm.mux_total = 0;
|
2014-07-21 17:43:38 +01:00
|
|
|
|
|
|
|
|
strncpy(b->pins[10].name, "IO10", 8);
|
2014-07-31 13:20:27 +01:00
|
|
|
b->pins[10].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
|
2014-07-21 17:43:38 +01:00
|
|
|
b->pins[10].gpio.pinmap = 41;
|
|
|
|
|
b->pins[10].gpio.parent_id = 0;
|
|
|
|
|
b->pins[10].gpio.mux_total = 2;
|
|
|
|
|
b->pins[10].gpio.mux[0].pin = 263;
|
|
|
|
|
b->pins[10].gpio.mux[0].value = 1;
|
|
|
|
|
b->pins[10].gpio.mux[1].pin = 240;
|
|
|
|
|
b->pins[10].gpio.mux[1].value = 0;
|
2014-07-31 14:53:03 +01:00
|
|
|
b->pins[10].spi.pinmap = 5;
|
|
|
|
|
b->pins[10].spi.mux_total = 2;
|
|
|
|
|
b->pins[10].spi.mux[0].pin = 263;
|
|
|
|
|
b->pins[10].spi.mux[0].value = 1;
|
|
|
|
|
b->pins[10].spi.mux[1].pin = 240;
|
|
|
|
|
b->pins[10].spi.mux[1].value = 1;
|
2014-07-21 17:43:38 +01:00
|
|
|
|
|
|
|
|
strncpy(b->pins[11].name, "IO11", 8);
|
2014-07-31 13:20:27 +01:00
|
|
|
b->pins[11].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
|
2014-07-21 17:43:38 +01:00
|
|
|
b->pins[11].gpio.pinmap = 43;
|
|
|
|
|
b->pins[11].gpio.parent_id = 0;
|
|
|
|
|
b->pins[11].gpio.mux_total = 2;
|
|
|
|
|
b->pins[11].gpio.mux[0].pin = 262;
|
|
|
|
|
b->pins[11].gpio.mux[0].value = 1;
|
|
|
|
|
b->pins[11].gpio.mux[1].pin = 241;
|
|
|
|
|
b->pins[11].gpio.mux[1].value = 0;
|
2014-07-31 13:20:27 +01:00
|
|
|
b->pins[11].spi.pinmap = 5;
|
|
|
|
|
b->pins[11].spi.mux_total = 2;
|
|
|
|
|
b->pins[11].spi.mux[0].pin = 262;
|
|
|
|
|
b->pins[11].spi.mux[0].value = 1;
|
|
|
|
|
b->pins[11].spi.mux[1].pin = 241;
|
2014-07-31 14:53:03 +01:00
|
|
|
b->pins[11].spi.mux[1].value = 1;
|
2014-07-21 17:43:38 +01:00
|
|
|
|
|
|
|
|
strncpy(b->pins[12].name, "IO12", 8);
|
2014-07-31 13:20:27 +01:00
|
|
|
b->pins[12].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
|
2014-07-21 17:43:38 +01:00
|
|
|
b->pins[12].gpio.pinmap = 42;
|
|
|
|
|
b->pins[12].gpio.parent_id = 0;
|
|
|
|
|
b->pins[12].gpio.mux_total = 1;
|
|
|
|
|
b->pins[12].gpio.mux[0].pin = 242;
|
|
|
|
|
b->pins[12].gpio.mux[0].value = 0;
|
2014-07-31 13:20:27 +01:00
|
|
|
b->pins[12].spi.pinmap = 5;
|
|
|
|
|
b->pins[12].spi.mux_total = 1;
|
|
|
|
|
b->pins[12].spi.mux[0].pin = 242;
|
|
|
|
|
b->pins[12].spi.mux[0].value = 1;
|
2014-07-21 17:43:38 +01:00
|
|
|
|
|
|
|
|
strncpy(b->pins[13].name, "IO13", 8);
|
2014-07-31 13:20:27 +01:00
|
|
|
b->pins[13].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
|
2014-07-21 17:43:38 +01:00
|
|
|
b->pins[13].gpio.pinmap = 40;
|
|
|
|
|
b->pins[13].gpio.parent_id = 0;
|
|
|
|
|
b->pins[13].gpio.mux_total = 1;
|
|
|
|
|
b->pins[13].gpio.mux[0].pin = 243;
|
|
|
|
|
b->pins[13].gpio.mux[0].value = 0;
|
2014-07-31 14:53:03 +01:00
|
|
|
b->pins[13].spi.pinmap = 5;
|
|
|
|
|
b->pins[13].spi.mux_total = 1;
|
|
|
|
|
b->pins[13].spi.mux[0].pin = 243;
|
|
|
|
|
b->pins[13].spi.mux[0].value = 1;
|
2014-07-21 17:43:38 +01:00
|
|
|
|
2014-07-28 17:51:28 +01:00
|
|
|
strncpy(b->pins[14].name, "A0", 8);
|
2014-07-29 15:51:42 +01:00
|
|
|
b->pins[14].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
|
2014-07-28 17:51:28 +01:00
|
|
|
b->pins[14].aio.pinmap = 0;
|
|
|
|
|
b->pins[14].aio.mux_total = 1;
|
|
|
|
|
b->pins[14].aio.mux[0].pin = 200;
|
|
|
|
|
b->pins[14].aio.mux[0].value = 1;
|
2014-07-29 15:51:42 +01:00
|
|
|
b->pins[14].gpio.pinmap = 44;
|
|
|
|
|
b->pins[14].gpio.mux_total = 1;
|
|
|
|
|
b->pins[14].gpio.mux[0].pin = 200;
|
|
|
|
|
b->pins[14].gpio.mux[0].value = 0;
|
2014-07-28 17:51:28 +01:00
|
|
|
|
|
|
|
|
strncpy(b->pins[15].name, "A1", 8);
|
2014-07-29 15:51:42 +01:00
|
|
|
b->pins[15].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
|
2014-07-28 17:51:28 +01:00
|
|
|
b->pins[15].aio.pinmap = 1;
|
|
|
|
|
b->pins[15].aio.mux_total = 1;
|
|
|
|
|
b->pins[15].aio.mux[0].pin = 201;
|
|
|
|
|
b->pins[15].aio.mux[0].value = 1;
|
2014-07-29 15:51:42 +01:00
|
|
|
b->pins[15].gpio.pinmap = 45;
|
|
|
|
|
b->pins[15].gpio.mux_total = 1;
|
|
|
|
|
b->pins[15].gpio.mux[0].pin = 201;
|
|
|
|
|
b->pins[15].gpio.mux[0].value = 0;
|
2014-07-28 17:51:28 +01:00
|
|
|
|
|
|
|
|
strncpy(b->pins[16].name, "A2", 8);
|
2014-07-29 15:51:42 +01:00
|
|
|
b->pins[16].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
|
2014-07-28 17:51:28 +01:00
|
|
|
b->pins[16].aio.pinmap = 2;
|
|
|
|
|
b->pins[16].aio.mux_total = 1;
|
|
|
|
|
b->pins[16].aio.mux[0].pin = 202;
|
|
|
|
|
b->pins[16].aio.mux[0].value = 1;
|
2014-07-29 15:51:42 +01:00
|
|
|
b->pins[16].gpio.pinmap = 46;
|
|
|
|
|
b->pins[16].gpio.mux_total = 1;
|
|
|
|
|
b->pins[16].gpio.mux[0].pin = 202;
|
|
|
|
|
b->pins[16].gpio.mux[0].value = 0;
|
2014-07-28 17:51:28 +01:00
|
|
|
|
|
|
|
|
strncpy(b->pins[17].name, "A3", 8);
|
2014-07-29 15:51:42 +01:00
|
|
|
b->pins[17].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
|
2014-07-28 17:51:28 +01:00
|
|
|
b->pins[17].aio.pinmap = 3;
|
|
|
|
|
b->pins[17].aio.mux_total = 1;
|
|
|
|
|
b->pins[17].aio.mux[0].pin = 203;
|
|
|
|
|
b->pins[17].aio.mux[0].value = 1;
|
2014-07-29 15:51:42 +01:00
|
|
|
b->pins[17].gpio.pinmap = 47;
|
|
|
|
|
b->pins[17].gpio.mux_total = 1;
|
|
|
|
|
b->pins[17].gpio.mux[0].pin = 203;
|
|
|
|
|
b->pins[17].gpio.mux[0].value = 0;
|
2014-07-28 17:51:28 +01:00
|
|
|
|
2014-07-24 14:02:53 +01:00
|
|
|
strncpy(b->pins[18].name, "A4", 8);
|
2014-07-29 15:51:42 +01:00
|
|
|
b->pins[18].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,1,0};
|
2014-07-24 14:02:53 +01:00
|
|
|
b->pins[18].i2c.pinmap = 1;
|
|
|
|
|
b->pins[18].i2c.mux_total = 1;
|
|
|
|
|
b->pins[18].i2c.mux[0].pin = 204;
|
|
|
|
|
b->pins[18].i2c.mux[0].value = 0;
|
2014-07-28 17:51:28 +01:00
|
|
|
b->pins[18].aio.pinmap = 4;
|
|
|
|
|
b->pins[18].aio.mux_total = 1;
|
|
|
|
|
b->pins[18].aio.mux[0].pin = 204;
|
|
|
|
|
b->pins[18].aio.mux[0].value = 1;
|
2014-07-29 15:51:42 +01:00
|
|
|
b->pins[18].gpio.pinmap = 14;
|
|
|
|
|
b->pins[18].gpio.mux_total = 1;
|
|
|
|
|
b->pins[18].gpio.mux[0].pin = 204;
|
|
|
|
|
b->pins[18].gpio.mux[0].value = 0;
|
2014-07-24 14:02:53 +01:00
|
|
|
|
|
|
|
|
strncpy(b->pins[19].name, "A5", 8);
|
2014-07-29 15:51:42 +01:00
|
|
|
b->pins[19].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,1,0};
|
2014-07-24 14:02:53 +01:00
|
|
|
b->pins[19].i2c.pinmap = 1;
|
|
|
|
|
b->pins[19].i2c.mux_total = 1;
|
|
|
|
|
b->pins[19].i2c.mux[0].pin = 205;
|
|
|
|
|
b->pins[19].i2c.mux[0].value = 0;
|
2014-07-28 17:51:28 +01:00
|
|
|
b->pins[19].aio.pinmap = 5;
|
|
|
|
|
b->pins[19].aio.mux_total = 1;
|
|
|
|
|
b->pins[19].aio.mux[0].pin = 205;
|
|
|
|
|
b->pins[19].aio.mux[0].value = 1;
|
2014-07-29 15:51:42 +01:00
|
|
|
b->pins[19].gpio.pinmap = 165;
|
|
|
|
|
b->pins[19].gpio.mux_total = 1;
|
|
|
|
|
b->pins[19].gpio.mux[0].pin = 205;
|
|
|
|
|
b->pins[19].gpio.mux[0].value = 0;
|
2014-07-24 14:02:53 +01:00
|
|
|
|
2014-07-11 14:31:38 +01:00
|
|
|
//BUS DEFINITIONS
|
2014-07-24 11:59:36 +01:00
|
|
|
b->i2c_bus_count = 9;
|
|
|
|
|
b->def_i2c_bus = 6;
|
|
|
|
|
int ici;
|
|
|
|
|
for (ici = 0; ici < 9; ici++) {
|
|
|
|
|
b->i2c_bus[ici].bus_id = -1;
|
|
|
|
|
}
|
|
|
|
|
b->i2c_bus[6].bus_id = 6;
|
|
|
|
|
b->i2c_bus[6].sda = 18;
|
|
|
|
|
b->i2c_bus[6].scl = 19;
|
2014-07-11 14:31:38 +01:00
|
|
|
|
|
|
|
|
b->spi_bus_count = 1;
|
|
|
|
|
b->def_spi_bus = 0;
|
2014-07-31 13:20:27 +01:00
|
|
|
b->spi_bus[0].bus_id = 5;
|
|
|
|
|
b->spi_bus[0].slave_s = 1;
|
2014-07-11 14:31:38 +01:00
|
|
|
b->spi_bus[0].cs = 10;
|
|
|
|
|
b->spi_bus[0].mosi = 11;
|
|
|
|
|
b->spi_bus[0].miso = 12;
|
|
|
|
|
b->spi_bus[0].sclk = 13;
|
|
|
|
|
|
2014-10-19 16:25:47 +01:00
|
|
|
b->uart_dev_count = 1;
|
|
|
|
|
b->def_uart_dev = 0;
|
|
|
|
|
b->uart_dev[0].rx = 0;
|
|
|
|
|
b->uart_dev[0].tx = 1;
|
|
|
|
|
|
2014-07-21 13:59:32 +01:00
|
|
|
int il;
|
2014-09-25 14:31:04 +01:00
|
|
|
for (il =0; il < MRAA_INTEL_EDISON_PINCOUNT; il++) {
|
2014-07-21 13:59:32 +01:00
|
|
|
pinmodes[il].gpio.sysfs = -1;
|
|
|
|
|
pinmodes[il].gpio.mode = -1;
|
|
|
|
|
pinmodes[il].pwm.sysfs = -1;
|
|
|
|
|
pinmodes[il].pwm.mode = -1;
|
|
|
|
|
pinmodes[il].i2c.sysfs = -1;
|
|
|
|
|
pinmodes[il].i2c.mode = -1;
|
|
|
|
|
pinmodes[il].spi.sysfs = -1;
|
|
|
|
|
pinmodes[il].spi.mode = -1;
|
|
|
|
|
pinmodes[il].uart.sysfs = -1;
|
|
|
|
|
pinmodes[il].uart.mode = -1;
|
|
|
|
|
}
|
|
|
|
|
pinmodes[0].gpio.sysfs = 130;
|
|
|
|
|
pinmodes[0].gpio.mode = 0;
|
|
|
|
|
pinmodes[0].uart.sysfs = 130;
|
|
|
|
|
pinmodes[0].uart.mode = 1;
|
|
|
|
|
pinmodes[1].gpio.sysfs = 131;
|
|
|
|
|
pinmodes[1].gpio.mode = 0;
|
|
|
|
|
pinmodes[1].uart.sysfs = 131;
|
|
|
|
|
pinmodes[1].uart.mode = 1;
|
|
|
|
|
pinmodes[2].gpio.sysfs = 128;
|
|
|
|
|
pinmodes[2].gpio.mode = 0;
|
|
|
|
|
pinmodes[2].uart.sysfs = 128;
|
|
|
|
|
pinmodes[2].uart.mode = 1;
|
|
|
|
|
pinmodes[3].gpio.sysfs = 12;
|
|
|
|
|
pinmodes[3].gpio.mode = 0;
|
|
|
|
|
pinmodes[3].pwm.sysfs = 12;
|
|
|
|
|
pinmodes[3].pwm.mode = 1;
|
|
|
|
|
|
|
|
|
|
pinmodes[4].gpio.sysfs = 129;
|
|
|
|
|
pinmodes[4].gpio.mode = 0;
|
|
|
|
|
pinmodes[4].uart.sysfs = 129;
|
|
|
|
|
pinmodes[4].uart.mode = 1;
|
|
|
|
|
pinmodes[5].gpio.sysfs = 13;
|
|
|
|
|
pinmodes[5].gpio.mode = 0;
|
|
|
|
|
pinmodes[5].pwm.sysfs = 13;
|
|
|
|
|
pinmodes[5].pwm.mode = 1;
|
|
|
|
|
pinmodes[6].gpio.sysfs = 182;
|
|
|
|
|
pinmodes[6].gpio.mode = 0;
|
|
|
|
|
pinmodes[6].pwm.sysfs = 182;
|
|
|
|
|
pinmodes[6].pwm.mode = 1;
|
|
|
|
|
|
|
|
|
|
//7 and 8 are provided by something on i2c, very simplepinmodes[3].gpio.sysfs = 12;
|
|
|
|
|
pinmodes[9].gpio.sysfs = 183;
|
|
|
|
|
pinmodes[9].gpio.mode = 0;
|
|
|
|
|
pinmodes[9].pwm.sysfs = 183;
|
|
|
|
|
pinmodes[9].pwm.mode = 1;
|
|
|
|
|
|
|
|
|
|
pinmodes[10].gpio.sysfs = 41;
|
|
|
|
|
pinmodes[10].gpio.mode = 0;
|
|
|
|
|
pinmodes[10].spi.sysfs = 111; // Different pin provides, switched at mux level.
|
|
|
|
|
pinmodes[10].spi.mode = 1;
|
|
|
|
|
|
|
|
|
|
pinmodes[11].gpio.sysfs = 43;
|
|
|
|
|
pinmodes[11].gpio.mode = 0;
|
|
|
|
|
pinmodes[11].spi.sysfs = 115; // Different pin provides, switched at mux level.
|
|
|
|
|
pinmodes[11].spi.mode = 1;
|
|
|
|
|
|
|
|
|
|
pinmodes[12].gpio.sysfs = 42;
|
|
|
|
|
pinmodes[12].gpio.mode = 0;
|
|
|
|
|
pinmodes[12].spi.sysfs = 114; // Different pin provides, switched at mux level.
|
|
|
|
|
pinmodes[12].spi.mode = 1;
|
|
|
|
|
|
|
|
|
|
pinmodes[13].gpio.sysfs = 40;
|
|
|
|
|
pinmodes[13].gpio.mode = 0;
|
|
|
|
|
pinmodes[13].spi.sysfs = 109; // Different pin provides, switched at mux level.
|
|
|
|
|
pinmodes[13].spi.mode = 1;
|
|
|
|
|
//Everything else but A4 A5 LEAVE
|
|
|
|
|
pinmodes[18].gpio.sysfs = 14;
|
|
|
|
|
pinmodes[18].gpio.mode = 0;
|
|
|
|
|
pinmodes[18].i2c.sysfs = 28;
|
|
|
|
|
pinmodes[18].i2c.mode = 1;
|
|
|
|
|
|
|
|
|
|
pinmodes[19].gpio.sysfs = 165;
|
|
|
|
|
pinmodes[19].gpio.mode = 0;
|
|
|
|
|
pinmodes[19].i2c.sysfs = 27;
|
|
|
|
|
pinmodes[19].i2c.mode = 1;
|
|
|
|
|
|
2014-07-11 14:31:38 +01:00
|
|
|
return b;
|
|
|
|
|
}
|