33 lines
807 B
C
33 lines
807 B
C
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/*
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* Author: Nascs <nascs@radxa.com>
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* Copyright (c) 2023 Radxa Limited.
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*
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* SPDX-License-Identifier: MIT
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "mraa_internal.h"
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#define MRAA_RADXA_CM3_GPIO_COUNT 28
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#define MRAA_RADXA_CM3_I2C_COUNT 3
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#define MRAA_RADXA_CM3_SPI_COUNT 2
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#define MRAA_RADXA_CM3_UART_COUNT 1
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#define MRAA_RADXA_CM3_PWM_COUNT 9
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#define MRAA_RADXA_CM3_AIO_COUNT 1
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#define MRAA_RADXA_CM3_PIN_COUNT 40
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#define PLATFORM_NAME_RADXA_CM3_IO "Radxa Compute Module 3(CM3) IO Board"
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#define PLATFORM_NAME_RADXA_CM3_IO_2 "Radxa CM3 IO Board"
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#define PLATFORM_NAME_RADXA_CM3_RPI_CM4_IO "Radxa CM3 RPI CM4 IO" // The core board of the Radxa CM3 is compatible with the RPI CM4 IO backplane.
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mraa_board_t *
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mraa_radxa_cm3();
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#ifdef __cplusplus
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}
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#endif
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