From 05d4a917e5d9af616fc3e926f61a378a415fb209 Mon Sep 17 00:00:00 2001 From: Arun Ravindran Date: Wed, 19 Apr 2017 11:52:01 +0300 Subject: [PATCH] joule: Update the documentation on SPI The existing documentation shows the MISO and MOSI pins wrongly. As per the hardware document available at http://www.intel.com/content/dam/support/us/en/documents/ joule-products/intel-joule-dev-kit-hardware-guide.pdf pin2 should be MISO and pin 4, MOSI. Signed-off-by: Arun Ravindran Signed-off-by: Brendan Le Foll --- docs/joule.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/joule.md b/docs/joule.md index f908bfd..13d4775 100644 --- a/docs/joule.md +++ b/docs/joule.md @@ -17,11 +17,11 @@ Interface notes Two SPI buses are available, with one chipselect each. Pins listed are MRAA numbered pins. Other chip selects are available if enabled in BIOS/EEPROM but cannot be enabled as BIOS options. You will need the spidev kernel module -loaded, Ostro-XT does this by default. +loaded, Ostro-XT and ref-os-iot does this by default. Bus 0 (32765) -MOSI = 2 -MISO = 4 +MOSI = 4 +MISO = 2 CS = 6 CLK = 10