From 084883c210a3b495fc7b52ae9702599a161dd86b Mon Sep 17 00:00:00 2001 From: Karena Anum Kamaruzaman Date: Fri, 22 Jan 2016 17:02:58 +0200 Subject: [PATCH] Enable CherryHills (Braswell) support for GPIO Enable the GPIOs for Cherryhills (Braswell). Signed-off-by: Karena Anum Kamaruzaman Signed-off-by: Constantin Musca Signed-off-by: Brendan Le Foll --- Android.mk | 3 +- api/mraa/types.h | 1 + include/x86/intel_cherryhills.h | 41 ++++++++++++++ src/CMakeLists.txt | 3 + src/x86/intel_cherryhills.c | 99 +++++++++++++++++++++++++++++++++ src/x86/x86.c | 6 ++ 6 files changed, 152 insertions(+), 1 deletion(-) create mode 100644 include/x86/intel_cherryhills.h create mode 100644 src/x86/intel_cherryhills.c diff --git a/Android.mk b/Android.mk index 43bc38d..24ca1d6 100644 --- a/Android.mk +++ b/Android.mk @@ -35,7 +35,8 @@ LOCAL_SRC_FILES := \ src/x86/intel_de3815.c \ src/x86/intel_nuc5.c \ src/x86/intel_sofia_3gr.c \ - src/x86/intel_minnow_byt_compatible.c + src/x86/intel_minnow_byt_compatible.c \ + src/x86/intel_cherryhills.c # glob.c pulled in from NetBSD project (BSD 3-clause License) LOCAL_SRC_FILES += \ diff --git a/api/mraa/types.h b/api/mraa/types.h index 27c489d..9311e60 100644 --- a/api/mraa/types.h +++ b/api/mraa/types.h @@ -48,6 +48,7 @@ typedef enum { MRAA_INTEL_NUC5 = 8, /**< The Intel 5th generations Broadwell NUCs */ MRAA_96BOARDS = 9, /**< Linaro 96boards */ MRAA_INTEL_SOFIA_3GR = 10, /**< The Intel SoFIA 3GR */ + MRAA_INTEL_CHERRYHILLS = 11, /**< The Intel Braswell Cherryhills */ // USB platform extenders start at 256 MRAA_FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */ diff --git a/include/x86/intel_cherryhills.h b/include/x86/intel_cherryhills.h new file mode 100644 index 0000000..09bddcf --- /dev/null +++ b/include/x86/intel_cherryhills.h @@ -0,0 +1,41 @@ +/* + * Author: Karena Anum Kamaruzaman + * Copyright (c) 2016 Intel Corporation. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "mraa_internal.h" + +// +1 as pins are "1 indexed" +#define MRAA_INTEL_CHERRYHILLS_PINCOUNT (5 + 1) + +mraa_board_t* +mraa_intel_cherryhills(); + +#ifdef __cplusplus +} +#endif diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 05b546c..14410a6 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -28,6 +28,7 @@ set (mraa_LIB_X86_SRCS_NOAUTO ${PROJECT_SOURCE_DIR}/src/x86/intel_nuc5.c ${PROJECT_SOURCE_DIR}/src/x86/intel_minnow_byt_compatible.c ${PROJECT_SOURCE_DIR}/src/x86/intel_sofia_3gr.c + ${PROJECT_SOURCE_DIR}/src/x86/intel_cherryhills.c ) message (INFO " - Adding support for platform ${MRAAPLATFORMFORCE}") @@ -49,6 +50,8 @@ if (NOT ${MRAAPLATFORMFORCE} STREQUAL "ALL") set (mraa_LIB_X86_SRCS_NOAUTO ${PROJECT_SOURCE_DIR}/src/x86/x86.c ${PROJECT_SOURCE_DIR}/src/x86/intel_nuc5.c) elseif (${MRAAPLATFORMFORCE} STREQUAL "MRAA_INTEL_SOFIA_3GR") set (mraa_LIB_X86_SRCS_NOAUTO ${PROJECT_SOURCE_DIR}/src/x86/x86.c ${PROJECT_SOURCE_DIR}/src/x86/intel_sofia_3gr.c) + elseif (${MRAAPLATFORMFORCE} STREQUAL "MRAA_INTEL_CHERRYHILLS") + set (mraa_LIB_X86_SRCS_NOAUTO ${PROJECT_SOURCE_DIR}/src/x86/x86.c ${PROJECT_SOURCE_DIR}/src/x86/intel_cherryhills.c) else () message (ERROR " - Unknown x86 platform enabled!") endif () diff --git a/src/x86/intel_cherryhills.c b/src/x86/intel_cherryhills.c new file mode 100644 index 0000000..b797c94 --- /dev/null +++ b/src/x86/intel_cherryhills.c @@ -0,0 +1,99 @@ +/* + * Author: Karena Anum Kamaruzaman + * Copyright (c) 2016 Intel Corporation. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include + +#include "common.h" +#include "x86/intel_cherryhills.h" + +#define PLATFORM_NAME "Braswell Cherry Hill" + +mraa_board_t* +mraa_intel_cherryhills() +{ + mraa_board_t* b = (mraa_board_t*) calloc(1, sizeof(mraa_board_t)); + if (b == NULL) { + return NULL; + } + + b->platform_name = PLATFORM_NAME; + b->phy_pin_count = MRAA_INTEL_CHERRYHILLS_PINCOUNT; + b->aio_count = 0; + b->adc_raw = 0; + b->adc_supported = 0; + + b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t) * MRAA_INTEL_CHERRYHILLS_PINCOUNT); + if (b->pins == NULL) { + goto error; + } + + b->adv_func = (mraa_adv_func_t*) calloc(1, sizeof(mraa_adv_func_t)); + if (b->adv_func == NULL) { + free(b->pins); + goto error; + } + + int pos = 0; + //Physical header where these pins are: J3E5 + strncpy(b->pins[pos].name, "GSUS6", 8); + b->pins[pos].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; + b->pins[pos].gpio.pinmap = 416; + b->pins[pos].gpio.mux_total = 0; + pos++; + + strncpy(b->pins[pos].name, "GSUS8", 8); + b->pins[pos].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; + b->pins[pos].gpio.pinmap = 409; + b->pins[pos].gpio.mux_total = 0; + pos++; + + strncpy(b->pins[pos].name, "GSUS7", 8); + b->pins[pos].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; + b->pins[pos].gpio.pinmap = 414; + b->pins[pos].gpio.mux_total = 0; + pos++; + + //Physical header where these pins are: J3E3 + strncpy(b->pins[pos].name, "GSUS0", 8); + b->pins[pos].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; + b->pins[pos].gpio.pinmap = 406; + b->pins[pos].gpio.mux_total = 0; + pos++; + + strncpy(b->pins[pos].name, "GSUS1", 8); + b->pins[pos].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }; + b->pins[pos].gpio.pinmap = 410; + b->pins[pos].gpio.mux_total = 0; + pos++; + + return b; +error: + syslog(LOG_CRIT, "Cherryhills(Braswell): Platform failed to initialise"); + free(b); + return NULL; +} diff --git a/src/x86/x86.c b/src/x86/x86.c index 57c4daf..50cf210 100644 --- a/src/x86/x86.c +++ b/src/x86/x86.c @@ -35,6 +35,7 @@ #include "x86/intel_nuc5.h" #include "x86/intel_minnow_byt_compatible.h" #include "x86/intel_sofia_3gr.h" +#include "x86/intel_cherryhills.h" mraa_platform_t mraa_x86_platform() @@ -78,6 +79,9 @@ mraa_x86_platform() } else if (strncasecmp(line, "MinnowBoard Turbot", 18) == 0) { platform_type = MRAA_INTEL_MINNOWBOARD_MAX; plat = mraa_intel_minnowboard_byt_compatible(1); + } else if (strncasecmp(line, "Braswell Cherry Hill", 20) == 0) { + platform_type = MRAA_INTEL_CHERRYHILLS; + plat = mraa_intel_cherryhills(); } else { syslog(LOG_ERR, "Platform not supported, not initialising"); platform_type = MRAA_UNKNOWN_PLATFORM; @@ -114,6 +118,8 @@ mraa_x86_platform() plat = mraa_intel_nuc5(); #elif defined(xMRAA_INTEL_SOFIA_3GR) plat = mraa_intel_sofia_3gr(); + #elif defined(xMRAA_INTEL_CHERRYHILLS) + plat = mraa_intel_cherryhills(); #else #error "Not using a valid platform value from mraa_platform_t - cannot compile" #endif