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platform: add Radxa ROCK 3C platform support

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Signed-off-by: Nascs <nascs@radxa.com>
This commit is contained in:
nascs
2023-06-30 03:08:08 +00:00
committed by Tom Ingleby
parent 809c3d6a3c
commit 09cea58214
6 changed files with 262 additions and 0 deletions
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34
api/mraa/types.h
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@@ -69,6 +69,7 @@ typedef enum {
MRAA_UPXTREME = 24, /**< The UPXTREME Board */
MRAA_INTEL_ILK = 25, /**< Intel Learning Kit */
MRAA_SIEMENS_IOT2050 = 26, /**< Siemens IOT2050 board */
MRAA_RADXA_ROCK_3C = 27, /**< Radxa ROCK 3 Model C */
// USB platform extenders start at 256
MRAA_FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */
@@ -175,6 +176,39 @@ typedef enum {
MRAA_INTEL_EDISON_GP81 = 55
} mraa_intel_edison_t;
/**
* Radxa ROCK 3 Model C GPIO numbering enum
*/
typedef enum {
MRAA_RADXA_ROCK_3C_PIN3 = 3,
MRAA_RADXA_ROCK_3C_PIN5 = 5,
MRAA_RADXA_ROCK_3C_PIN7 = 7,
MRAA_RADXA_ROCK_3C_PIN8 = 8,
MRAA_RADXA_ROCK_3C_PIN10 = 10,
MRAA_RADXA_ROCK_3C_PIN11 = 11,
MRAA_RADXA_ROCK_3C_PIN12 = 12,
MRAA_RADXA_ROCK_3C_PIN13 = 13,
MRAA_RADXA_ROCK_3C_PIN15 = 15,
MRAA_RADXA_ROCK_3C_PIN16 = 16,
MRAA_RADXA_ROCK_3C_PIN18 = 18,
MRAA_RADXA_ROCK_3C_PIN19 = 19,
MRAA_RADXA_ROCK_3C_PIN21 = 21,
MRAA_RADXA_ROCK_3C_PIN22 = 22,
MRAA_RADXA_ROCK_3C_PIN23 = 23,
MRAA_RADXA_ROCK_3C_PIN24 = 24,
MRAA_RADXA_ROCK_3C_PIN27 = 27,
MRAA_RADXA_ROCK_3C_PIN28 = 28,
MRAA_RADXA_ROCK_3C_PIN29 = 29,
MRAA_RADXA_ROCK_3C_PIN31 = 31,
MRAA_RADXA_ROCK_3C_PIN32 = 32,
MRAA_RADXA_ROCK_3C_PIN33 = 33,
MRAA_RADXA_ROCK_3C_PIN35 = 35,
MRAA_RADXA_ROCK_3C_PIN36 = 36,
MRAA_RADXA_ROCK_3C_PIN37 = 37,
MRAA_RADXA_ROCK_3C_PIN38 = 38,
MRAA_RADXA_ROCK_3C_PIN40 = 40
} mraa_radxa_rock_3c_wiring_t;
/**
* ROCKPI4 GPIO numbering enum
*/

34
api/mraa/types.hpp
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@@ -63,6 +63,7 @@ typedef enum {
ROCKPI4 = 20, /**< Radxa ROCK PI 4 Models A/B/C */
INTEL_UPXTREME = 24, /**< The UPXTREME Board */
SIEMENS_IOT2050 = 26, /**< Siemens IOT2050 board */
RADXA_ROCK_3C = 27, /**< Radxa ROCK 3 Model C */
FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */
@@ -167,6 +168,39 @@ typedef enum {
INTEL_EDISON_GP81 = 55
} IntelEdison;
/**
* Radxa ROCK 3 Model C GPIO numbering enum
*/
typedef enum {
RADXA_ROCK_3C_PIN3 = 3,
RADXA_ROCK_3C_PIN5 = 5,
RADXA_ROCK_3C_PIN7 = 7,
RADXA_ROCK_3C_PIN8 = 8,
RADXA_ROCK_3C_PIN10 = 10,
RADXA_ROCK_3C_PIN11 = 11,
RADXA_ROCK_3C_PIN12 = 12,
RADXA_ROCK_3C_PIN13 = 13,
RADXA_ROCK_3C_PIN15 = 15,
RADXA_ROCK_3C_PIN16 = 16,
RADXA_ROCK_3C_PIN18 = 18,
RADXA_ROCK_3C_PIN19 = 19,
RADXA_ROCK_3C_PIN21 = 21,
RADXA_ROCK_3C_PIN22 = 22,
RADXA_ROCK_3C_PIN23 = 23,
RADXA_ROCK_3C_PIN24 = 24,
RADXA_ROCK_3C_PIN27 = 27,
RADXA_ROCK_3C_PIN28 = 28,
RADXA_ROCK_3C_PIN29 = 29,
RADXA_ROCK_3C_PIN31 = 31,
RADXA_ROCK_3C_PIN32 = 32,
RADXA_ROCK_3C_PIN33 = 33,
RADXA_ROCK_3C_PIN35 = 35,
RADXA_ROCK_3C_PIN36 = 36,
RADXA_ROCK_3C_PIN37 = 37,
RADXA_ROCK_3C_PIN38 = 38,
RADXA_ROCK_3C_PIN40 = 40
} RadxaRock3CWiring;
/**
* ROCKPI4 GPIO numbering enum
*/

30
include/arm/radxa_rock_3c.h Normal file
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@@ -0,0 +1,30 @@
/*
* Author: Nascs <nascs@radxa.com>
* Copyright (c) Radxa Limited.
*
* SPDX-License-Identifier: MIT
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "mraa_internal.h"
#define MRAA_RADXA_ROCK_3C_GPIO_COUNT 27
#define MRAA_RADXA_ROCK_3C_I2C_COUNT 2
#define MRAA_RADXA_ROCK_3C_SPI_COUNT 1
#define MRAA_RADXA_ROCK_3C_UART_COUNT 5
#define MRAA_RADXA_ROCK_3C_PWM_COUNT 7
#define MRAA_RADXA_ROCK_3C_AIO_COUNT 0
#define MRAA_RADXA_ROCK_3C_PIN_COUNT 40
#define PLATFORM_NAME_RADXA_ROCK_3C "Radxa ROCK3 Model C"
mraa_board_t *
mraa_radxa_rock_3c();
#ifdef __cplusplus
}
#endif

1
src/CMakeLists.txt
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@@ -107,6 +107,7 @@ set (mraa_LIB_ARM_SRCS_NOAUTO
${PROJECT_SOURCE_DIR}/src/arm/phyboard.c
${PROJECT_SOURCE_DIR}/src/arm/banana.c
${PROJECT_SOURCE_DIR}/src/arm/de_nano_soc.c
${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_3c.c
${PROJECT_SOURCE_DIR}/src/arm/rockpi4.c
${PROJECT_SOURCE_DIR}/src/arm/adlink_ipi.c
${PROJECT_SOURCE_DIR}/src/arm/siemens/iot2050.c

6
src/arm/arm.c
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@@ -10,6 +10,7 @@
#include <string.h>
#include "arm/96boards.h"
#include "arm/radxa_rock_3c.h"
#include "arm/rockpi4.h"
#include "arm/de_nano_soc.h"
#include "arm/banana.h"
@@ -91,6 +92,8 @@ mraa_arm_platform()
platform_type = MRAA_96BOARDS;
else if (mraa_file_contains("/proc/device-tree/model", "Avnet Ultra96 Rev1"))
platform_type = MRAA_96BOARDS;
else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_ROCK_3C))
platform_type = MRAA_RADXA_ROCK_3C;
else if (mraa_file_contains("/proc/device-tree/model", "ROCK Pi 4") ||
mraa_file_contains("/proc/device-tree/model", "ROCK PI 4") ||
mraa_file_contains("/proc/device-tree/model", "ROCK 4")
@@ -120,6 +123,9 @@ mraa_arm_platform()
case MRAA_96BOARDS:
plat = mraa_96boards();
break;
case MRAA_RADXA_ROCK_3C:
plat = mraa_radxa_rock_3c();
break;
case MRAA_ROCKPI4:
plat = mraa_rockpi4();
break;

157
src/arm/radxa_rock_3c.c Normal file
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@@ -0,0 +1,157 @@
/*
* Author: Nascs <nascs@radxa.com>
* Copyright (c) Radxa Limited.
*
* SPDX-License-Identifier: MIT
*/
#include <mraa/common.h>
#include <stdarg.h>
#include <stdlib.h>
#include <string.h>
#include <sys/mman.h>
#include "arm/radxa_rock_3c.h"
#include "common.h"
const char* radxa_rock_3c_serialdev[MRAA_RADXA_ROCK_3C_UART_COUNT] = { "/dev/ttyS2", "/dev/ttyS3", "/dev/ttyS4", "/dev/ttyS5", "/dev/ttyS9" };
void
mraa_radxa_rock_3c_pininfo(mraa_board_t* board, int index, int gpio_chip, int gpio_line, mraa_pincapabilities_t pincapabilities_t, char* pin_name)
{
if (index > board->phy_pin_count)
return;
mraa_pininfo_t* pininfo = &board->pins[index];
strncpy(pininfo->name, pin_name, MRAA_PIN_NAME_SIZE);
if(pincapabilities_t.gpio == 1) {
pininfo->gpio.gpio_chip = gpio_chip;
pininfo->gpio.gpio_line = gpio_line;
}
pininfo->capabilities = pincapabilities_t;
pininfo->gpio.mux_total = 0;
}
mraa_board_t*
mraa_radxa_rock_3c()
{
mraa_board_t* b = (mraa_board_t*) calloc(1, sizeof(mraa_board_t));
if (b == NULL) {
return NULL;
}
b->adv_func = (mraa_adv_func_t*) calloc(1, sizeof(mraa_adv_func_t));
if (b->adv_func == NULL) {
free(b);
return NULL;
}
// pin mux for buses are setup by default by kernel so tell mraa to ignore them
b->no_bus_mux = 1;
b->phy_pin_count = MRAA_RADXA_ROCK_3C_PIN_COUNT + 1;
b->platform_name = PLATFORM_NAME_RADXA_ROCK_3C;
b->chardev_capable = 1;
// UART
b->uart_dev_count = MRAA_RADXA_ROCK_3C_UART_COUNT;
b->def_uart_dev = 0;
b->uart_dev[0].index = 2;
b->uart_dev[1].index = 3;
b->uart_dev[2].index = 4;
b->uart_dev[3].index = 5;
b->uart_dev[4].index = 9;
b->uart_dev[0].device_path = (char*) radxa_rock_3c_serialdev[0];
b->uart_dev[1].device_path = (char*) radxa_rock_3c_serialdev[1];
b->uart_dev[2].device_path = (char*) radxa_rock_3c_serialdev[2];
b->uart_dev[3].device_path = (char*) radxa_rock_3c_serialdev[3];
b->uart_dev[4].device_path = (char*) radxa_rock_3c_serialdev[4];
// I2C
b->i2c_bus_count = MRAA_RADXA_ROCK_3C_I2C_COUNT;
b->def_i2c_bus = 0;
b->i2c_bus[0].bus_id = 3;
b->i2c_bus[1].bus_id = 4;
// SPI
b->spi_bus_count = MRAA_RADXA_ROCK_3C_SPI_COUNT;
b->def_spi_bus = 0;
b->spi_bus[0].bus_id = 3;
// PWM
b->pwm_dev_count = MRAA_RADXA_ROCK_3C_PWM_COUNT;
b->pwm_default_period = 500;
b->pwm_max_period = 2147483;
b->pwm_min_period = 1;
b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t) * b->phy_pin_count);
if (b->pins == NULL) {
free(b->adv_func);
free(b);
return NULL;
}
b->pins[16].pwm.parent_id = 8; // pwm8-m0
b->pins[16].pwm.mux_total = 0;
b->pins[18].pwm.parent_id = 9; // pwm9-m0
b->pins[18].pwm.mux_total = 0;
b->pins[21].pwm.parent_id = 12; // pwm12-m1
b->pins[21].pwm.mux_total = 0;
b->pins[24].pwm.parent_id = 13; // pwm13-m1
b->pins[24].pwm.mux_total = 0;
b->pins[7].pwm.parent_id = 14; // pwm14-m0
b->pins[7].pwm.mux_total = 0;
b->pins[23].pwm.parent_id = 14; // pwm14-m1
b->pins[23].pwm.mux_total = 0;
b->pins[13].pwm.parent_id = 15; // pwm15-m0
b->pins[13].pwm.mux_total = 0;
b->pins[19].pwm.parent_id = 15; // pwm15-m1
b->pins[19].pwm.mux_total = 0;
mraa_radxa_rock_3c_pininfo(b, 0, -1, -1, (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, "INVALID");
mraa_radxa_rock_3c_pininfo(b, 1, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3");
mraa_radxa_rock_3c_pininfo(b, 2, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "5V");
mraa_radxa_rock_3c_pininfo(b, 3, 1, 0, (mraa_pincapabilities_t){1,0,0,0,0,1,0,1}, "GPIO0_D1"); // Hardware pull-up on this pin
mraa_radxa_rock_3c_pininfo(b, 4, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "5V");
mraa_radxa_rock_3c_pininfo(b, 5, 1, 1, (mraa_pincapabilities_t){1,0,0,0,0,1,0,1}, "GPIO0_D0"); // Hardware pull-up on this pin
mraa_radxa_rock_3c_pininfo(b, 6, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_3c_pininfo(b, 7, 3, 20, (mraa_pincapabilities_t){1,1,1,0,0,0,0,0}, "GPIO3_C4");
mraa_radxa_rock_3c_pininfo(b, 8, 0, 25, (mraa_pincapabilities_t){1,0,0,0,0,0,0,1}, "GPIO0_D1"); // Used by fiq_debugger
mraa_radxa_rock_3c_pininfo(b, 9, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_3c_pininfo(b, 10, 0, 24, (mraa_pincapabilities_t){1,0,0,0,0,0,0,1}, "GPIO0_D0"); // Used by fiq_debugger
mraa_radxa_rock_3c_pininfo(b, 11, 3, 1, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_A1");
mraa_radxa_rock_3c_pininfo(b, 12, 3, 3, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_A3");
mraa_radxa_rock_3c_pininfo(b, 13, 3, 2, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_A2");
mraa_radxa_rock_3c_pininfo(b, 14, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_3c_pininfo(b, 15, 3, 8, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO03_B0");
mraa_radxa_rock_3c_pininfo(b, 16, 3, 9, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO03_B1");
mraa_radxa_rock_3c_pininfo(b, 17, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3");
mraa_radxa_rock_3c_pininfo(b, 18, 3, 10, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO3_B2");
mraa_radxa_rock_3c_pininfo(b, 19, 4, 19, (mraa_pincapabilities_t){1,1,1,0,1,0,0,0}, "GPIO4_C3");
mraa_radxa_rock_3c_pininfo(b, 20, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_3c_pininfo(b, 21, 4, 21, (mraa_pincapabilities_t){1,1,1,0,1,0,0,1}, "GPIO4_C5");
mraa_radxa_rock_3c_pininfo(b, 22, 3, 17, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_C1");
mraa_radxa_rock_3c_pininfo(b, 23, 4, 18, (mraa_pincapabilities_t){1,1,1,0,1,0,0,0}, "GPIO4_C2");
mraa_radxa_rock_3c_pininfo(b, 24, 4, 22, (mraa_pincapabilities_t){1,1,1,0,1,0,0,1}, "GPIO4_C6");
mraa_radxa_rock_3c_pininfo(b, 25, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_3c_pininfo(b, 26, -1, -1, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO4_D1");
mraa_radxa_rock_3c_pininfo(b, 27, 4, 10, (mraa_pincapabilities_t){1,1,0,0,0,1,0,0}, "GPIO4_B2");
mraa_radxa_rock_3c_pininfo(b, 28, 4, 11, (mraa_pincapabilities_t){1,1,0,0,0,1,0,0}, "GPIO4_B3");
mraa_radxa_rock_3c_pininfo(b, 29, 3, 11, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_B3");
mraa_radxa_rock_3c_pininfo(b, 30, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_3c_pininfo(b, 31, 3, 12, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_B4");
mraa_radxa_rock_3c_pininfo(b, 32, 3, 18, (mraa_pincapabilities_t){1,1,0,0,0,0,0,1}, "GPIO3_C2");
mraa_radxa_rock_3c_pininfo(b, 33, 3, 19, (mraa_pincapabilities_t){1,1,0,0,0,0,0,1}, "GPIO3_C3");
mraa_radxa_rock_3c_pininfo(b, 34, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_3c_pininfo(b, 35, 3, 4, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_A4");
mraa_radxa_rock_3c_pininfo(b, 36, 3, 7, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_A7");
mraa_radxa_rock_3c_pininfo(b, 37, 1, 4, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GPIO1_A4"); // can not set gpio pinmux
mraa_radxa_rock_3c_pininfo(b, 38, 3, 6, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_A6");
mraa_radxa_rock_3c_pininfo(b, 39, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_3c_pininfo(b, 40, 3, 5, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_A5");
return b;
}