From 3b01af1da15cf703c9b17f14e0fe5720e2449977 Mon Sep 17 00:00:00 2001 From: Thomas Ingleby Date: Thu, 30 Oct 2014 12:03:24 +0000 Subject: [PATCH] pwm: add period limits, warn over syslog Added minimum, maximum and default period settings to board definitions PWM will now have a default period as defined in the board defintion. When using pwm_write() writing 1.0f or above will default to 100%. Signed-off-by: Thomas Ingleby --- api/mraa/common.h | 3 +++ src/intel_de3815.c | 3 +++ src/intel_edison_fab_c.c | 7 +++++++ src/intel_galileo_rev_d.c | 3 +++ src/intel_galileo_rev_g.c | 3 +++ src/pwm/pwm.c | 9 +++++++++ 6 files changed, 28 insertions(+) diff --git a/api/mraa/common.h b/api/mraa/common.h index 72ce90c..48495fe 100644 --- a/api/mraa/common.h +++ b/api/mraa/common.h @@ -183,6 +183,9 @@ typedef struct { unsigned int def_uart_dev; /**< Position in array of defult uart */ unsigned int uart_dev_count; /**< Usable spi Count */ mraa_uart_dev_t uart_dev[6]; /**< Array of UARTs */ + int pwm_default_period; /**< The default PWM period is US */ + int pwm_max_period; /**< Maximum period in us */ + int pwm_min_period; /**< Minimum period in us */ mraa_pininfo_t* pins; /**< Pointer to pin array */ /*@}*/ } mraa_board_t; diff --git a/src/intel_de3815.c b/src/intel_de3815.c index 3da6a8b..512ba57 100644 --- a/src/intel_de3815.c +++ b/src/intel_de3815.c @@ -43,6 +43,9 @@ mraa_intel_de3815() b->aio_count = 0; b->adc_raw = 0; b->adc_supported = 0; + b->pwm_default_period = 500; + b->pwm_max_period = 2147483; + b->pwm_min_period = 1; b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t)*MRAA_INTEL_DE3815_PINCOUNT); diff --git a/src/intel_edison_fab_c.c b/src/intel_edison_fab_c.c index 667e2e0..6e2e8d8 100644 --- a/src/intel_edison_fab_c.c +++ b/src/intel_edison_fab_c.c @@ -493,6 +493,10 @@ mraa_intel_edsion_miniboard(mraa_board_t* b) b->phy_pin_count = 56; b->gpio_count = 56; // A bit of a hack I suppose b->aio_count = 0; + b->pwm_default_period = 5000; + b->pwm_max_period = 218453; + b->pwm_min_period = 1; + b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t)*56); @@ -890,6 +894,9 @@ mraa_intel_edison_fab_c() b->adc_raw = 12; b->adc_supported = 10; + b->pwm_default_period = 5000; + b->pwm_max_period = 218453; + b->pwm_min_period = 1; strncpy(b->pins[0].name, "IO0", 8); b->pins[0].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,1}; diff --git a/src/intel_galileo_rev_d.c b/src/intel_galileo_rev_d.c index ae0d70d..631c198 100644 --- a/src/intel_galileo_rev_d.c +++ b/src/intel_galileo_rev_d.c @@ -42,6 +42,9 @@ mraa_intel_galileo_rev_d() b->adc_raw = 12; b->adc_supported = 10; + b->pwm_default_period = 500; + b->pwm_max_period = 7968; + b->pwm_min_period = 1; b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t)*MRAA_INTEL_GALILEO_REV_D_PINCOUNT); diff --git a/src/intel_galileo_rev_g.c b/src/intel_galileo_rev_g.c index 3b85776..d6e06ac 100644 --- a/src/intel_galileo_rev_g.c +++ b/src/intel_galileo_rev_g.c @@ -177,6 +177,9 @@ mraa_intel_galileo_gen2() b->aio_count = 6; b->adc_raw = 12; b->adc_supported = 10; + b->pwm_default_period = 5000; + b->pwm_max_period = 41666; + b->pwm_min_period = 666; advance_func->gpio_dir_pre = &mraa_intel_galileo_gen2_dir_pre; advance_func->i2c_init_pre = &mraa_intel_galileo_gen2_i2c_init_pre; diff --git a/src/pwm/pwm.c b/src/pwm/pwm.c index cfcf4be..16d0f33 100644 --- a/src/pwm/pwm.c +++ b/src/pwm/pwm.c @@ -201,6 +201,7 @@ mraa_pwm_init_raw(int chipin, int pin) return NULL; } dev->owner = 1; + mraa_pwm_period_us(dev, plat->pwm_default_period); close(export_f); } mraa_pwm_setup_duty_fp(dev); @@ -210,6 +211,9 @@ mraa_pwm_init_raw(int chipin, int pin) mraa_result_t mraa_pwm_write(mraa_pwm_context dev, float percentage) { + if (percentage >= 1.0f) { + return mraa_pwm_write_duty(dev, mraa_pwm_read_period(dev)); + } return mraa_pwm_write_duty(dev, percentage * mraa_pwm_read_period(dev)); } @@ -235,6 +239,11 @@ mraa_pwm_period_ms(mraa_pwm_context dev, int ms) mraa_result_t mraa_pwm_period_us(mraa_pwm_context dev, int us) { + if (us < plat->pwm_min_period || + us > plat->pwm_max_period) { + syslog(LOG_ERR, "pwm: period value outside platform range"); + return MRAA_ERROR_INVALID_PARAMETER; + } return mraa_pwm_write_period(dev, us*1000); }