Raspberries/mraa
Private
Public Access
2
0
Fork 0
Code Activity

radxa cm5 io: remove useless pwm pins

Browse Source 
Signed-off-by: Nascs <nascs@radxa.com>
This commit is contained in:
Nascs
2024-03-28 07:26:54 +00:00
committed by Tom Ingleby
parent 9374cc49c6
commit 4754c5ef29
2 changed files with 2 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
include/arm/radxa_cm5_io.h
View File

@@ -17,7 +17,7 @@ extern "C" {
#define MRAA_RADXA_CM5_IO_I2C_COUNT 4 #define MRAA_RADXA_CM5_IO_I2C_COUNT 4
#define MRAA_RADXA_CM5_IO_SPI_COUNT 1 #define MRAA_RADXA_CM5_IO_SPI_COUNT 1
#define MRAA_RADXA_CM5_IO_UART_COUNT 2 #define MRAA_RADXA_CM5_IO_UART_COUNT 2
#define MRAA_RADXA_CM5_IO_PWM_COUNT 9 #define MRAA_RADXA_CM5_IO_PWM_COUNT 7
#define MRAA_RADXA_CM5_IO_AIO_COUNT 1 #define MRAA_RADXA_CM5_IO_AIO_COUNT 1
#define MRAA_RADXA_CM5_IO_PIN_COUNT 40 #define MRAA_RADXA_CM5_IO_PIN_COUNT 40
#define PLATFORM_NAME_RADXA_CM5_IO "Radxa CM5 IO" #define PLATFORM_NAME_RADXA_CM5_IO "Radxa CM5 IO"

8
src/arm/radxa_cm5_io.c
View File

@@ -93,15 +93,9 @@ mraa_radxa_cm5_io()
b->pins[3].pwm.parent_id = 10; // PWM10-M2 b->pins[3].pwm.parent_id = 10; // PWM10-M2
b->pins[3].pwm.mux_total = 0; b->pins[3].pwm.mux_total = 0;
b->pins[3].pwm.pinmap = 0; b->pins[3].pwm.pinmap = 0;
b->pins[16].pwm.parent_id = 11; // PWM11-M0
b->pins[16].pwm.mux_total = 0;
b->pins[16].pwm.pinmap = 0;
b->pins[24].pwm.parent_id = 14; // PWM14-M1 b->pins[24].pwm.parent_id = 14; // PWM14-M1
b->pins[24].pwm.mux_total = 0; b->pins[24].pwm.mux_total = 0;
b->pins[24].pwm.pinmap = 0; b->pins[24].pwm.pinmap = 0;
b->pins[28].pwm.parent_id = 14; // PWM14-M2
b->pins[28].pwm.mux_total = 0;
b->pins[28].pwm.pinmap = 0;
b->pins[29].pwm.parent_id = 7; // PWM7-M0 b->pins[29].pwm.parent_id = 7; // PWM7-M0
b->pins[29].pwm.mux_total = 0; b->pins[29].pwm.mux_total = 0;
b->pins[29].pwm.pinmap = 0; b->pins[29].pwm.pinmap = 0;
@@ -142,7 +136,7 @@ mraa_radxa_cm5_io()
mraa_radxa_cm5_io_pininfo(b, 13, 4, 5, (mraa_pincapabilities_t){1,1,0,0,0,1,0,1}, "GPIO4_A5"); mraa_radxa_cm5_io_pininfo(b, 13, 4, 5, (mraa_pincapabilities_t){1,1,0,0,0,1,0,1}, "GPIO4_A5");
mraa_radxa_cm5_io_pininfo(b, 14, -1, -1, (mraa_pincapabilities_t){1,0,0,0, 0,0,0,0}, "GND"); mraa_radxa_cm5_io_pininfo(b, 14, -1, -1, (mraa_pincapabilities_t){1,0,0,0, 0,0,0,0}, "GND");
mraa_radxa_cm5_io_pininfo(b, 15, 4, 4, (mraa_pincapabilities_t){1,1,0,0,0,1,0,0}, "GPIO4_A4"); mraa_radxa_cm5_io_pininfo(b, 15, 4, 4, (mraa_pincapabilities_t){1,1,0,0,0,1,0,0}, "GPIO4_A4");
mraa_radxa_cm5_io_pininfo(b, 16, 1, 20, (mraa_pincapabilities_t){1,1,1,0,1,1,0,0}, "GPIO1_C4"); mraa_radxa_cm5_io_pininfo(b, 16, 1, 20, (mraa_pincapabilities_t){1,1,0,0,1,1,0,0}, "GPIO1_C4"); // Conflict with the fan's pwm11-m3
mraa_radxa_cm5_io_pininfo(b, 17, -1, -1, (mraa_pincapabilities_t){1,0,0,0, 0,0,0,0}, "3V3"); mraa_radxa_cm5_io_pininfo(b, 17, -1, -1, (mraa_pincapabilities_t){1,0,0,0, 0,0,0,0}, "3V3");
mraa_radxa_cm5_io_pininfo(b, 18, 1, 29, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO1_D5"); mraa_radxa_cm5_io_pininfo(b, 18, 1, 29, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO1_D5");
mraa_radxa_cm5_io_pininfo(b, 19, 4, 1, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO4_A1"); mraa_radxa_cm5_io_pininfo(b, 19, 4, 1, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO4_A1");