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platform: adjusting the order of pwm pins of radxa borads

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Signed-off-by: Nascs <nascs@radxa.com>
This commit is contained in:
Nascs
2024-03-26 07:02:21 +00:00
committed by Tom Ingleby
parent 258bfcf3da
commit 4e11858355
6 changed files with 85 additions and 85 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
src/arm/radxa_cm3.c
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@@ -96,24 +96,24 @@ mraa_radxa_cm3()
return NULL;
}
b->pins[13].pwm.parent_id = 0; // pwm0-m0
b->pins[13].pwm.mux_total = 0;
b->pins[11].pwm.parent_id = 0; // pwm0-m1
b->pins[11].pwm.mux_total = 0;
b->pins[5].pwm.parent_id = 1; // pwm1-m1
b->pins[5].pwm.mux_total = 0;
b->pins[3].pwm.parent_id = 2; // pwm2-m1
b->pins[3].pwm.mux_total = 0;
b->pins[37].pwm.parent_id = 3; // pwm3
b->pins[37].pwm.mux_total = 0;
b->pins[5].pwm.parent_id = 1; // pwm1-m1
b->pins[5].pwm.mux_total = 0;
b->pins[11].pwm.parent_id = 0; // pwm0-m1
b->pins[11].pwm.mux_total = 0;
b->pins[13].pwm.parent_id = 0; // pwm0-m0
b->pins[13].pwm.mux_total = 0;
b->pins[15].pwm.parent_id = 4; // pwm4
b->pins[15].pwm.mux_total = 0;
b->pins[31].pwm.parent_id = 6; // pwm6
b->pins[31].pwm.mux_total = 0;
b->pins[33].pwm.parent_id = 15; // pwm7
b->pins[33].pwm.mux_total = 0;
b->pins[32].pwm.parent_id = 11; // pwm11-m1
b->pins[32].pwm.mux_total = 0;
b->pins[33].pwm.parent_id = 15; // pwm7
b->pins[33].pwm.mux_total = 0;
b->pins[37].pwm.parent_id = 3; // pwm3
b->pins[37].pwm.mux_total = 0;
mraa_radxa_cm3_pininfo(b, 0, -1, -1, (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, "INVALID");
mraa_radxa_cm3_pininfo(b, 1, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3.3V");

24
src/arm/radxa_cm5_io.c
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@@ -90,27 +90,27 @@ mraa_radxa_cm5_io()
return NULL;
}
b->pins[38].pwm.parent_id = 0; // PWM0-M1
b->pins[38].pwm.mux_total = 0;
b->pins[38].pwm.pinmap = 0;
b->pins[31].pwm.parent_id = 6; // PWM6-M0
b->pins[31].pwm.mux_total = 0;
b->pins[31].pwm.pinmap = 0;
b->pins[29].pwm.parent_id = 7; // PWM7-M0
b->pins[29].pwm.mux_total = 0;
b->pins[29].pwm.pinmap = 0;
b->pins[16].pwm.parent_id = 11; // PWM11-M0
b->pins[16].pwm.mux_total = 0;
b->pins[16].pwm.pinmap = 0;
b->pins[32].pwm.parent_id = 13; // PWM13-M2
b->pins[32].pwm.mux_total = 0;
b->pins[32].pwm.pinmap = 0;
b->pins[24].pwm.parent_id = 11; // PWM14-M1
b->pins[24].pwm.mux_total = 0;
b->pins[24].pwm.pinmap = 0;
b->pins[29].pwm.parent_id = 7; // PWM7-M0
b->pins[29].pwm.mux_total = 0;
b->pins[29].pwm.pinmap = 0;
b->pins[31].pwm.parent_id = 6; // PWM6-M0
b->pins[31].pwm.mux_total = 0;
b->pins[31].pwm.pinmap = 0;
b->pins[32].pwm.parent_id = 13; // PWM13-M2
b->pins[32].pwm.mux_total = 0;
b->pins[32].pwm.pinmap = 0;
b->pins[36].pwm.parent_id = 15; // PWM15-M2
b->pins[36].pwm.mux_total = 0;
b->pins[36].pwm.pinmap = 0;
b->pins[38].pwm.parent_id = 0; // PWM0-M1
b->pins[38].pwm.mux_total = 0;
b->pins[38].pwm.pinmap = 0;
// AIO
b->aio_count = MRAA_RADXA_CM5_IO_AIO_COUNT;

12
src/arm/radxa_rock_3a.c
View File

@@ -101,12 +101,18 @@ mraa_radxa_rock_3a()
b->pins[7].pwm.parent_id = 12; // PWM12_M0
b->pins[7].pwm.mux_total = 0;
b->pins[7].pwm.parent_id = 1; // PWM1_M1
b->pins[7].pwm.mux_total = 0;
b->pins[11].pwm.parent_id = 14; // PWM14_M0
b->pins[11].pwm.mux_total = 0;
b->pins[13].pwm.parent_id = 15; // PWM15_IR_M0
b->pins[13].pwm.mux_total = 0;
b->pins[15].pwm.parent_id = 1; // PWM1_M0
b->pins[15].pwm.mux_total = 0;
b->pins[16].pwm.parent_id = 2; // PWM2_M1
b->pins[16].pwm.mux_total = 0;
b->pins[18].pwm.parent_id = 9; // PWM9_M0
b->pins[18].pwm.mux_total = 0;
b->pins[19].pwm.parent_id = 15; // PWM15_IR_M1
b->pins[19].pwm.mux_total = 0;
b->pins[21].pwm.parent_id = 12; // PWM12_M1
@@ -115,12 +121,6 @@ mraa_radxa_rock_3a()
b->pins[23].pwm.mux_total = 0;
b->pins[24].pwm.parent_id = 13; // PWM13_M1
b->pins[24].pwm.mux_total = 0;
b->pins[18].pwm.parent_id = 9; // PWM9_M0
b->pins[18].pwm.mux_total = 0;
b->pins[16].pwm.parent_id = 2; // PWM2_M1
b->pins[16].pwm.mux_total = 0;
b->pins[7].pwm.parent_id = 1; // PWM1_M1
b->pins[7].pwm.mux_total = 0;
// hardware V1.3/V1.31
mraa_radxa_rock_3a_pininfo(b, 0, -1, -1, (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, "INVALID");

28
src/arm/radxa_rock_3b.c
View File

@@ -97,28 +97,28 @@ mraa_radxa_rock_3b()
return NULL;
}
b->pins[15].pwm.parent_id = 1; // pwm1-m0
b->pins[15].pwm.mux_total = 0;
b->pins[7].pwm.parent_id = 1; // pwm1-m1
b->pins[7].pwm.mux_total = 0;
b->pins[22].pwm.parent_id = 2; // pwm2-m0
b->pins[22].pwm.mux_total = 0;
b->pins[11].pwm.parent_id = 14; // pwm14-m0
b->pins[11].pwm.mux_total = 0;
b->pins[13].pwm.parent_id = 15; // pwm15-m0
b->pins[13].pwm.mux_total = 0;
b->pins[15].pwm.parent_id = 1; // pwm1-m0
b->pins[15].pwm.mux_total = 0;
b->pins[16].pwm.parent_id = 2; // pwm2-m1
b->pins[16].pwm.mux_total = 0;
b->pins[18].pwm.parent_id = 9; // pwm9-m0
b->pins[18].pwm.mux_total = 0;
b->pins[21].pwm.parent_id = 12; // pwm12-m1
b->pins[21].pwm.mux_total = 0;
b->pins[24].pwm.parent_id = 13; // pwm13-m1
b->pins[24].pwm.mux_total = 0;
b->pins[11].pwm.parent_id = 14; // pwm14-m0
b->pins[11].pwm.mux_total = 0;
b->pins[23].pwm.parent_id = 14; // pwm14-m1
b->pins[23].pwm.mux_total = 0;
b->pins[13].pwm.parent_id = 15; // pwm15-m0
b->pins[13].pwm.mux_total = 0;
b->pins[19].pwm.parent_id = 15; // pwm15-m1
b->pins[19].pwm.mux_total = 0;
b->pins[21].pwm.parent_id = 12; // pwm12-m1
b->pins[21].pwm.mux_total = 0;
b->pins[22].pwm.parent_id = 2; // pwm2-m0
b->pins[22].pwm.mux_total = 0;
b->pins[23].pwm.parent_id = 14; // pwm14-m1
b->pins[23].pwm.mux_total = 0;
b->pins[24].pwm.parent_id = 13; // pwm13-m1
b->pins[24].pwm.mux_total = 0;
mraa_radxa_rock_3b_pininfo(b, 0, -1, -1, (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, "INVALID");
mraa_radxa_rock_3b_pininfo(b, 1, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3");

20
src/arm/radxa_rock_3c.c
View File

@@ -94,22 +94,22 @@ mraa_radxa_rock_3c()
return NULL;
}
b->pins[7].pwm.parent_id = 14; // pwm14-m0
b->pins[7].pwm.mux_total = 0;
b->pins[13].pwm.parent_id = 15; // pwm15-m0
b->pins[13].pwm.mux_total = 0;
b->pins[16].pwm.parent_id = 8; // pwm8-m0
b->pins[16].pwm.mux_total = 0;
b->pins[18].pwm.parent_id = 9; // pwm9-m0
b->pins[18].pwm.mux_total = 0;
b->pins[21].pwm.parent_id = 12; // pwm12-m1
b->pins[21].pwm.mux_total = 0;
b->pins[24].pwm.parent_id = 13; // pwm13-m1
b->pins[24].pwm.mux_total = 0;
b->pins[7].pwm.parent_id = 14; // pwm14-m0
b->pins[7].pwm.mux_total = 0;
b->pins[23].pwm.parent_id = 14; // pwm14-m1
b->pins[23].pwm.mux_total = 0;
b->pins[13].pwm.parent_id = 15; // pwm15-m0
b->pins[13].pwm.mux_total = 0;
b->pins[19].pwm.parent_id = 15; // pwm15-m1
b->pins[19].pwm.mux_total = 0;
b->pins[21].pwm.parent_id = 12; // pwm12-m1
b->pins[21].pwm.mux_total = 0;
b->pins[23].pwm.parent_id = 14; // pwm14-m1
b->pins[23].pwm.mux_total = 0;
b->pins[24].pwm.parent_id = 13; // pwm13-m1
b->pins[24].pwm.mux_total = 0;
mraa_radxa_rock_3c_pininfo(b, 0, -1, -1, (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, "INVALID");
mraa_radxa_rock_3c_pininfo(b, 1, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3");

66
src/arm/radxa_rock_5b.c
View File

@@ -87,48 +87,48 @@ mraa_radxa_rock_5b()
return NULL;
}
b->pins[36].pwm.parent_id = 2; // PWM2_M1
b->pins[36].pwm.mux_total = 0;
b->pins[36].pwm.pinmap = 0;
b->pins[38].pwm.parent_id = 3; // PWM3_M1
b->pins[38].pwm.mux_total = 0;
b->pins[38].pwm.pinmap = 0;
b->pins[18].pwm.parent_id = 5; // PWM5_M2
b->pins[18].pwm.mux_total = 0;
b->pins[18].pwm.pinmap = 0;
b->pins[28].pwm.parent_id = 6; // PWM6_M2
b->pins[28].pwm.mux_total = 0;
b->pins[28].pwm.pinmap = 0;
b->pins[27].pwm.parent_id = 7; // PWM7_M3
b->pins[27].pwm.mux_total = 0;
b->pins[27].pwm.pinmap = 0;
b->pins[33].pwm.parent_id = 8; // PWM8_M0
b->pins[33].pwm.mux_total = 0;
b->pins[33].pwm.pinmap = 0;
b->pins[12].pwm.parent_id = 12; // PWM12_M0
b->pins[12].pwm.mux_total = 0;
b->pins[12].pwm.pinmap = 0;
b->pins[35].pwm.parent_id = 13; // PWM13_M0
b->pins[35].pwm.mux_total = 0;
b->pins[35].pwm.pinmap = 0;
b->pins[31].pwm.parent_id = 13; // PWM13_M2
b->pins[31].pwm.mux_total = 0;
b->pins[31].pwm.pinmap = 0;
b->pins[32].pwm.parent_id = 14; // PWM14_M0
b->pins[32].pwm.mux_total = 0;
b->pins[32].pwm.pinmap = 0;
b->pins[3].pwm.parent_id = 15; // PWM15_M1
b->pins[3].pwm.mux_total = 0;
b->pins[3].pwm.pinmap = 0;
b->pins[5].pwm.parent_id = 14; // PWM14_M2
b->pins[5].pwm.mux_total = 0;
b->pins[5].pwm.pinmap = 0;
b->pins[7].pwm.parent_id = 15; // PWM15_M0
b->pins[7].pwm.mux_total = 0;
b->pins[7].pwm.pinmap = 0;
b->pins[3].pwm.parent_id = 15; // PWM15_M1
b->pins[3].pwm.mux_total = 0;
b->pins[3].pwm.pinmap = 0;
b->pins[12].pwm.parent_id = 12; // PWM12_M0
b->pins[12].pwm.mux_total = 0;
b->pins[12].pwm.pinmap = 0;
b->pins[18].pwm.parent_id = 5; // PWM5_M2
b->pins[18].pwm.mux_total = 0;
b->pins[18].pwm.pinmap = 0;
b->pins[27].pwm.parent_id = 7; // PWM7_M3
b->pins[27].pwm.mux_total = 0;
b->pins[27].pwm.pinmap = 0;
b->pins[28].pwm.parent_id = 6; // PWM6_M2
b->pins[28].pwm.mux_total = 0;
b->pins[28].pwm.pinmap = 0;
b->pins[29].pwm.parent_id = 7; // PWM15_M3
b->pins[29].pwm.mux_total = 0;
b->pins[29].pwm.pinmap = 0;
b->pins[31].pwm.parent_id = 13; // PWM13_M2
b->pins[31].pwm.mux_total = 0;
b->pins[31].pwm.pinmap = 0;
b->pins[32].pwm.parent_id = 14; // PWM14_M0
b->pins[32].pwm.mux_total = 0;
b->pins[32].pwm.pinmap = 0;
b->pins[33].pwm.parent_id = 8; // PWM8_M0
b->pins[33].pwm.mux_total = 0;
b->pins[33].pwm.pinmap = 0;
b->pins[35].pwm.parent_id = 13; // PWM13_M0
b->pins[35].pwm.mux_total = 0;
b->pins[35].pwm.pinmap = 0;
b->pins[36].pwm.parent_id = 2; // PWM2_M1
b->pins[36].pwm.mux_total = 0;
b->pins[36].pwm.pinmap = 0;
b->pins[38].pwm.parent_id = 3; // PWM3_M1
b->pins[38].pwm.mux_total = 0;
b->pins[38].pwm.pinmap = 0;
b->aio_count = MRAA_RADXA_ROCK_5B_AIO_COUNT;
b->adc_raw = 10;