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mock: added AIO pin and logic

Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
This commit is contained in:
Alex Tereschenko
2016-07-10 17:40:11 +02:00
committed by Brendan Le Foll
parent 917a1bd371
commit 63b244cfc3
6 changed files with 102 additions and 8 deletions

View File

@@ -12,17 +12,17 @@ Board configuration
-------------------
This feature is yet in the experimental mode and not all functionality is available.
Right now we simulate a single generic board with only GPIO (without ISR) working.
It also reports having an ADC with 10 (std)/12 (max) bit resolution, but the ADC
functionality itself is not yet implemented.
Right now we simulate a single generic board with GPIO (without ISR) and
an ADC with 10 (std)/12 (max) bit resolution, which returns random values on read.
We plan to develop it further and all [contributions](../CONTRIBUTING.md) are more than welcome.
See the table below for pin layout and features
| MRAA Number | Pin Name | Notes |
|-------------|----------|-----------------------------|
| 0 | GPIO0 | GPIO pin, no muxing, no ISR |
| MRAA Number | Pin Name | Notes |
|-------------|----------|---------------------------------------|
| 0 | GPIO0 | GPIO pin, no muxing, no ISR |
| 1 | ADC0 | AIO pin, returns random value on read |
Building
--------