diff --git a/api/mraa/types.h b/api/mraa/types.h index 1cfe013..78885ec 100644 --- a/api/mraa/types.h +++ b/api/mraa/types.h @@ -41,6 +41,7 @@ typedef enum { MRAA_INTEL_GALILEO_GEN2 = 1, /**< The Generation 2 Galileo platform (RevG/H) */ MRAA_INTEL_EDISON_FAB_C = 2, /**< The Intel Edison (FAB C) */ MRAA_INTEL_DE3815 = 3, /**< The Intel DE3815 Baytrail NUC */ + MRAA_INTEL_MINNOWBOARD_MAX = 4, /**< The Intel Minnow Board Max */ MRAA_UNKNOWN_PLATFORM = 99 /**< An unknown platform type, typically will load INTEL_GALILEO_GEN1 */ } mraa_platform_t; diff --git a/include/intel_minnow_max.h b/include/intel_minnow_max.h new file mode 100644 index 0000000..96c604d --- /dev/null +++ b/include/intel_minnow_max.h @@ -0,0 +1,41 @@ +/* + * Author: Thomas Ingleby + * Copyright (c) 2014 Intel Corporation. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "mraa_internal.h" + +// +1 as pins are "1 indexed" +#define MRAA_INTEL_MINNOW_MAX_PINCOUNT (26 + 1) + +mraa_board_t* +mraa_intel_minnow_max(); + +#ifdef __cplusplus +} +#endif diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index f1c2c1d..da8bb17 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -16,6 +16,7 @@ set (mraa_LIB_SRCS ${PROJECT_SOURCE_DIR}/src/intel_galileo_rev_g.c ${PROJECT_SOURCE_DIR}/src/intel_edison_fab_c.c ${PROJECT_SOURCE_DIR}/src/intel_de3815.c + ${PROJECT_SOURCE_DIR}/src/intel_minnow_max.c # autogenerated version file ${CMAKE_CURRENT_BINARY_DIR}/version.c ) diff --git a/src/intel_minnow_max.c b/src/intel_minnow_max.c new file mode 100644 index 0000000..611c452 --- /dev/null +++ b/src/intel_minnow_max.c @@ -0,0 +1,149 @@ +/* + * Author: Henry Bruce + * Copyright (c) 2014 Intel Corporation. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#include "common.h" +#include "intel_minnow_max.h" + +#define I2C_BUS_COUNT 10 +#define I2C_BUS_DEFAULT 7 + +unsigned int +mraa_set_pininfo(mraa_board_t* board, int mraa_index, char *name, mraa_pincapabilities_t caps, int sysfs_pin) +{ + if (mraa_index < board->phy_pin_count) { + mraa_pininfo_t* pin_info = &board->pins[mraa_index]; + strncpy(pin_info->name, name, 8); + pin_info->capabilites = caps; + if (caps.gpio) + pin_info->gpio.pinmap = sysfs_pin; + if (caps.i2c) { + pin_info->i2c.pinmap = 1; + pin_info->i2c.mux_total = 0; + } + if (caps.pwm) { + int controller = 0; + if (strncmp(name, "PWM", 3) == 0 && strlen(name) > 3 && isdigit(name[3])) + controller = name[3] - '0'; + pin_info->pwm.parent_id = controller; + pin_info->pwm.pinmap = 0; + pin_info->pwm.mux_total = 0; + } + return MRAA_SUCCESS; + } + return MRAA_ERROR_INVALID_RESOURCE; +} + +unsigned int +mraa_get_pin_index(mraa_board_t* board, char *name, int* pin_index) { + int i; + for (i = 0; i < board->phy_pin_count; ++i) { + if (strcmp(name, board->pins[i].name) == 0) { + *pin_index = i; + return MRAA_SUCCESS; + } + } + return MRAA_ERROR_INVALID_RESOURCE; +} + +mraa_board_t* +mraa_intel_minnow_max() +{ + mraa_board_t* b = (mraa_board_t*) malloc(sizeof(mraa_board_t)); + if (b == NULL) + return NULL; + + b->phy_pin_count = MRAA_INTEL_MINNOW_MAX_PINCOUNT; + //b->gpio_count = 14; + b->aio_count = 0; + b->adc_raw = 0; + b->adc_supported = 0; + + b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t)*MRAA_INTEL_MINNOW_MAX_PINCOUNT); + mraa_set_pininfo(b, 0, "INVALID", (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, -1); + mraa_set_pininfo(b, 1, "GND", (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, -1); + mraa_set_pininfo(b, 2, "GND", (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, -1); + mraa_set_pininfo(b, 3, "5v", (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, -1); + mraa_set_pininfo(b, 4, "3.3v", (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, -1); + mraa_set_pininfo(b, 5, "SPI_CS", (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, 220); + mraa_set_pininfo(b, 6, "UART1_TX", (mraa_pincapabilities_t){1,1,0,0,0,0,0,1}, 225); + mraa_set_pininfo(b, 7, "SPI_MISO", (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, 221); + mraa_set_pininfo(b, 8, "UART1_RX", (mraa_pincapabilities_t){1,1,0,0,0,0,0,1}, 224); + mraa_set_pininfo(b, 9, "SPI_MOSI", (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, 222); + mraa_set_pininfo(b, 10, "UART1_CT", (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, 227); + mraa_set_pininfo(b, 11, "SPI_CLK", (mraa_pincapabilities_t){1,1,0,0,0,0,0,1}, 223); + mraa_set_pininfo(b, 12, "UART1_RT", (mraa_pincapabilities_t){1,1,0,0,0,0,0,1}, 226); + mraa_set_pininfo(b, 13, "I2C_SCL", (mraa_pincapabilities_t){1,1,0,0,0,1,0,0}, 243); + mraa_set_pininfo(b, 14, "I2S_CLK", (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, 216); + mraa_set_pininfo(b, 15, "I2C_SDA", (mraa_pincapabilities_t){1,1,0,0,0,1,0,0}, 242); + mraa_set_pininfo(b, 16, "I2S_FRM", (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, 217); + mraa_set_pininfo(b, 17, "UART2_TX", (mraa_pincapabilities_t){1,1,0,0,0,0,0,1}, 229); + mraa_set_pininfo(b, 18, "I2S_DO", (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, 219); + mraa_set_pininfo(b, 19, "UART2_RX", (mraa_pincapabilities_t){1,1,0,0,0,0,0,1}, 228); + mraa_set_pininfo(b, 20, "I2S_DI", (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, 218); + mraa_set_pininfo(b, 21, "S5_0", (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, 82); + mraa_set_pininfo(b, 22, "PWM0", (mraa_pincapabilities_t){1,0,1,0,0,0,0,0}, 248); // Assume BIOS configured for PWM + mraa_set_pininfo(b, 23, "S5_1", (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, 83); + mraa_set_pininfo(b, 24, "PWM1", (mraa_pincapabilities_t){1,0,1,0,0,0,0,0}, 249); // Assume BIOS configured for PWM + mraa_set_pininfo(b, 25, "S5_4", (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, 84); + mraa_set_pininfo(b, 26, "IBL_8254", (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, 208); + + // Set number of i2c adaptors + // Got this from running 'i2cdetect -l' + b->i2c_bus_count = I2C_BUS_COUNT; + + // Disable all i2c adaptors + int ici; + for (ici = 0; ici < b->i2c_bus_count; ici++) { + b->i2c_bus[ici].bus_id = -1; + } + + // Configure i2c adaptor #7 and make it the default + int pin_index_sda, pin_index_scl; + if (mraa_get_pin_index(b, "I2C_SDA", &pin_index_sda) == MRAA_SUCCESS && + mraa_get_pin_index(b, "I2C_SCL", &pin_index_scl) == MRAA_SUCCESS) { + b->def_i2c_bus = I2C_BUS_DEFAULT; + b->i2c_bus[b->def_i2c_bus].bus_id = b->def_i2c_bus; + b->i2c_bus[b->def_i2c_bus].sda = pin_index_sda; + b->i2c_bus[b->def_i2c_bus].scl = pin_index_scl; + } + + // Configure PWM + b->pwm_default_period = 500; + b->pwm_max_period = 1000000000; + b->pwm_min_period = 1; + + b->spi_bus_count = 1; + b->def_spi_bus = 0; + b->spi_bus[0].bus_id = 0; + b->spi_bus[0].slave_s = 0; + b->spi_bus[0].cs = 5; + b->spi_bus[0].mosi = 9; + b->spi_bus[0].miso = 7; + b->spi_bus[0].sclk = 11; + + return b; +} diff --git a/src/mraa.c b/src/mraa.c index 1321a02..5b672db 100644 --- a/src/mraa.c +++ b/src/mraa.c @@ -28,11 +28,14 @@ #include #include +#define DEBUG + #include "mraa_internal.h" #include "intel_galileo_rev_d.h" #include "intel_galileo_rev_g.h" #include "intel_edison_fab_c.h" #include "intel_de3815.h" +#include "intel_minnow_max.h" #include "gpio.h" #include "version.h" @@ -92,6 +95,10 @@ mraa_init() platform_type = MRAA_INTEL_EDISON_FAB_C; } else if (strncmp(line, "DE3815", 6) == 0) { platform_type = MRAA_INTEL_DE3815; + } else if (strncmp(line, "NOTEBOOK", 8) == 0) { + platform_type = MRAA_INTEL_MINNOWBOARD_MAX; + } else if (strncasecmp(line, "MinnowBoard MAX", 15) == 0) { + platform_type = MRAA_INTEL_MINNOWBOARD_MAX; } else { platform_type = MRAA_INTEL_GALILEO_GEN1; } @@ -116,9 +123,13 @@ mraa_init() case MRAA_INTEL_DE3815: plat = mraa_intel_de3815(); break; + case MRAA_INTEL_MINNOWBOARD_MAX: + plat = mraa_intel_minnow_max(); + break; + default: plat = mraa_intel_galileo_rev_d(); - syslog(LOG_ERR, "Platform not found, initialising MRAA_INTEL_GALILEO_GEN1"); + syslog(LOG_ERR, "Platform not supported, initialising as MRAA_INTEL_GALILEO_GEN1"); } syslog(LOG_NOTICE, "libmraa initialised for platform %d", platform_type);