de-nano-soc: renamed platform to avoid ambiguity

Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>

README.md

@@ -40,7 +40,7 @@ ARM
 
 FPGA
 ----
-* [DE10-Nano](../master/docs/altera-socfpga.md)
+* [DE10-Nano](../master/docs/de_nano_soc.md)
 
 USB
 ---

api/mraa/types.h

@@ -46,16 +46,16 @@ typedef enum {
     MRAA_BEAGLEBONE = 6,            /**< The different BeagleBone Black Modes B/C */
     MRAA_BANANA = 7,                /**< Allwinner A20 based Banana Pi and Banana Pro */
     MRAA_INTEL_NUC5 = 8,            /**< The Intel 5th generations Broadwell NUCs */
-    MRAA_96BOARDS = 9,            /**< Linaro 96boards */
+    MRAA_96BOARDS = 9,              /**< Linaro 96boards */
     MRAA_INTEL_SOFIA_3GR = 10,      /**< The Intel SoFIA 3GR */
-    MRAA_INTEL_CHERRYHILLS = 11,     /**< The Intel Braswell Cherryhills */
+    MRAA_INTEL_CHERRYHILLS = 11,    /**< The Intel Braswell Cherryhills */
-    MRAA_UP = 12,                    /**< The UP Board */
+    MRAA_UP = 12,                   /**< The UP Board */
-    MRAA_INTEL_JOULE_EXPANSION = 13,      /**< The Intel Joule Expansion Board */
+    MRAA_INTEL_JOULE_EXPANSION = 13,/**< The Intel Joule Expansion Board */
 #if __STDC_VERSION__ >= 199901L
     MRAA_INTEL_GT_TUCHUCK = MRAA_INTEL_JOULE_EXPANSION, // deprecated
 #endif
     MRAA_PHYBOARD_WEGA = 14,        /**< The phyBOARD-Wega */
-    MRAA_ALTERA_SOCFPGA = 15,       /**< Terasic DE-Nano-SoC Board */
+    MRAA_DE_NANO_SOC = 15,          /**< Terasic DE-Nano-SoC Board */
 
     // USB platform extenders start at 256
     MRAA_FTDI_FT4222 = 256,         /**< FTDI FT4222 USB to i2c bridge */

api/mraa/types.hpp

@@ -51,9 +51,9 @@ typedef enum {
     INTEL_SOFIA_3GR = 10,      /**< The Intel SoFIA 3GR */
     INTEL_CHERRYHILLS = 11,    /**< The Intel Braswell Cherryhills */
     INTEL_UP = 12,             /**< The UP Board */
-    INTEL_JOULE_EXPANSION = 13,     /**< The Intel Joule Expansion Board */
+    INTEL_JOULE_EXPANSION = 13,/**< The Intel Joule Expansion Board */
     PHYBOARD_WEGA = 14,        /**< The phyBOARD-Wega */
-    MRAA_ALTERA_SOCFPGA = 15,  /**< Terasic DE-Nano-SoC Board */
+    DE_NANO_SOC = 15,          /**< Terasic DE-Nano-SoC Board */
 
     FTDI_FT4222 = 256,         /**< FTDI FT4222 USB to i2c bridge */
 

include/arm/de_nano_soc.h

@@ -33,10 +33,10 @@ extern "C" {
 // 1x32 Arduino header, 1x40 GPIO_0/JP1, 1x40 GPIO_1/JP7,
 // 9 LEDs (8 User + HPS_LED), 4 switches, 3 buttons (2 User + HPS_KEY)
 // 10 ADC pins
-#define MRAA_ALTERA_SOCFPGA_PINCOUNT 138
+#define MRAA_DE_NANO_SOC_PINCOUNT 138
 
 mraa_board_t *
-        mraa_altera_socfpga();
+        mraa_de_nano_soc();
 
 #ifdef __cplusplus
 }

src/CMakeLists.txt

@@ -83,7 +83,7 @@ set (mraa_LIB_ARM_SRCS_NOAUTO
   ${PROJECT_SOURCE_DIR}/src/arm/beaglebone.c
   ${PROJECT_SOURCE_DIR}/src/arm/phyboard.c
   ${PROJECT_SOURCE_DIR}/src/arm/banana.c
-  ${PROJECT_SOURCE_DIR}/src/arm/altera_socfpga.c
+  ${PROJECT_SOURCE_DIR}/src/arm/de_nano_soc.c
 )
 
 set (mraa_LIB_MOCK_SRCS_NOAUTO

src/arm/arm.c

@@ -27,7 +27,7 @@
 #include <string.h>
 
 #include "arm/96boards.h"
-#include "arm/altera_socfpga.h"
+#include "arm/de_nano_soc.h"
 #include "arm/banana.h"
 #include "arm/beaglebone.h"
 #include "arm/phyboard.h"
@@ -73,8 +73,8 @@ mraa_arm_platform()
                     else if (mraa_file_exist("/sys/class/leds/green:ph24:led1")) {
                         platform_type = MRAA_BANANA;
                     }
-                } else if (strstr(line, "Altera SOCFPGA")) {
+                } else if (strstr(line, "DE0/DE10-Nano-SoC")) {
-                        platform_type = MRAA_ALTERA_SOCFPGA;
+                        platform_type = MRAA_DE_NANO_SOC;
                 }
             }
         }
@@ -112,8 +112,8 @@ mraa_arm_platform()
         case MRAA_96BOARDS:
             plat = mraa_96boards();
             break;
-        case MRAA_ALTERA_SOCFPGA:
+        case MRAA_DE_NANO_SOC:
-            plat = mraa_altera_socfpga();
+            plat = mraa_de_nano_soc();
             break;
         default:
             plat = NULL;

src/arm/de_nano_soc.c

@@ -28,9 +28,9 @@
 #include <mraa/common.h>
 
 #include "common.h"
-#include "arm/altera_socfpga.h"
+#include "arm/de_nano_soc.h"
 
-#define PLATFORM_NAME "DE10-Nano-SoC"
+#define PLATFORM_NAME "DE0/DE10-Nano-SoC"
 #define SYSFS_CLASS_GPIO "/sys/class/gpio"
 #define DEBUGFS_PINMODE_PATH "/sys/kernel/debug/gpio"
 
@@ -49,28 +49,28 @@ static unsigned int mmap_count = 0;
 
 // MMAP stubbed functions
 mraa_result_t
-mraa_altera_socfpga_spi_init_pre(int index)
+mraa_de_nano_soc_spi_init_pre(int index)
 {
     return MRAA_SUCCESS;
 }
 
 mraa_result_t
-mraa_altera_socfpga_i2c_init_pre(unsigned int bus)
+mraa_de_nano_soc_i2c_init_pre(unsigned int bus)
 {
     return MRAA_SUCCESS;
 }
 
 mraa_result_t
-mraa_altera_socfpga_mmap_write(mraa_gpio_context dev, int value)
+mraa_de_nano_soc_mmap_write(mraa_gpio_context dev, int value)
 {
     return MRAA_SUCCESS;
 }
 
 static mraa_result_t
-mraa_altera_socfpga_mmap_unsetup()
+mraa_de_nano_soc_mmap_unsetup()
 {
     if (mmap_reg == NULL) {
-        syslog(LOG_ERR, "altera_socfpga mmap: null register cant unsetup");
+        syslog(LOG_ERR, "de_nano_soc mmap: null register cant unsetup");
         return MRAA_ERROR_INVALID_RESOURCE;
     }
     munmap(mmap_reg, mmap_size);
@@ -82,36 +82,36 @@ mraa_altera_socfpga_mmap_unsetup()
 }
 
 int
-mraa_altera_socfpga_mmap_read(mraa_gpio_context dev)
+mraa_de_nano_soc_mmap_read(mraa_gpio_context dev)
 {
     return 0;
 }
 
 mraa_result_t
-mraa_altera_socfpga_mmap_setup(mraa_gpio_context dev, mraa_boolean_t en)
+mraa_de_nano_soc_mmap_setup(mraa_gpio_context dev, mraa_boolean_t en)
 {
 
     if (dev == NULL) {
-        syslog(LOG_ERR, "altera_socfpga mmap: context not valid");
+        syslog(LOG_ERR, "de_nano_soc mmap: context not valid");
         return MRAA_ERROR_INVALID_HANDLE;
     }
 
     if (en == 0) {
         if (dev->mmap_write == NULL && dev->mmap_read == NULL) {
-            syslog(LOG_ERR, "altera_socfpga mmap: can't disable disabled mmap gpio");
+            syslog(LOG_ERR, "de_nano_soc mmap: can't disable disabled mmap gpio");
             return MRAA_ERROR_INVALID_PARAMETER;
         }
         dev->mmap_write = NULL;
         dev->mmap_read = NULL;
         mmap_count--;
         if (mmap_count == 0) {
-            return mraa_altera_socfpga_mmap_unsetup();
+            return mraa_de_nano_soc_mmap_unsetup();
         }
         return MRAA_SUCCESS;
     }
 
     if (dev->mmap_write != NULL && dev->mmap_read != NULL) {
-        syslog(LOG_ERR, "altera_socfpga mmap: can't enable enabled mmap gpio");
+        syslog(LOG_ERR, "de_nano_soc mmap: can't enable enabled mmap gpio");
         return MRAA_ERROR_INVALID_PARAMETER;
     }
 
@@ -120,28 +120,28 @@ mraa_altera_socfpga_mmap_setup(mraa_gpio_context dev, mraa_boolean_t en)
     // to prevent mmap'ing twice.
     if (mmap_reg == NULL) {
         if ((mmap_fd = open(MMAP_PATH, O_RDWR)) < 0) {
-            syslog(LOG_ERR, "altera_socfpga map: unable to open resource0 file");
+            syslog(LOG_ERR, "de_nano_soc map: unable to open resource0 file");
             return MRAA_ERROR_INVALID_HANDLE;
         }
 
 
         mmap_reg = (uint8_t*) mmap(NULL, mmap_size, PROT_READ | PROT_WRITE, MAP_FILE | MAP_SHARED, mmap_fd, FPGA_REGION_BASE);
         if (mmap_reg == MAP_FAILED) {
-            syslog(LOG_ERR, "altera_socfpga mmap: failed to mmap");
+            syslog(LOG_ERR, "de_nano_soc mmap: failed to mmap");
             mmap_reg = NULL;
             close(mmap_fd);
             return MRAA_ERROR_NO_RESOURCES;
         }
     }
-    dev->mmap_write = &mraa_altera_socfpga_mmap_write;
+    dev->mmap_write = &mraa_de_nano_soc_mmap_write;
-    dev->mmap_read = &mraa_altera_socfpga_mmap_read;
+    dev->mmap_read = &mraa_de_nano_soc_mmap_read;
     mmap_count++;
 
     return MRAA_SUCCESS;
 }
 
 mraa_board_t*
-mraa_altera_socfpga()
+mraa_de_nano_soc()
 {
     mraa_board_t* b = (mraa_board_t*) calloc(1, sizeof(mraa_board_t));
     if (b == NULL) {
@@ -149,7 +149,7 @@ mraa_altera_socfpga()
     }
 
     b->platform_name = PLATFORM_NAME;
-    b->phy_pin_count = MRAA_ALTERA_SOCFPGA_PINCOUNT;
+    b->phy_pin_count = MRAA_DE_NANO_SOC_PINCOUNT;
     b->gpio_count = 96; // update as needed when adding ADC pins
     b->aio_count = 8;
     //b->pwm_default_period = 5000;