Raspberries/mraa
Private
Public Access
2
0
Fork 0
Code Activity

arch: initial framework for supporting other architectures added.

Browse Source 
x86: all platforms moved into x86 directory

Signed-off-by: Thomas Ingleby <thomas.c.ingleby@intel.com>
This commit is contained in:
Thomas Ingleby
2014-11-21 00:01:08 +00:00
parent aff88114e5
commit b0a21e2c30
11 changed files with 129 additions and 62 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/x86/CMakeLists.txt Normal file
View File

@@ -0,0 +1,10 @@
message (INFO " - Adding x86 platforms")
set (mraa_LIB_SRCS_NOAUTO ${mraa_LIB_SRCS_NOAUTO}
${PROJECT_SOURCE_DIR}/src/x86/x86.c
${PROJECT_SOURCE_DIR}/src/x86/intel_galileo_rev_d.c
${PROJECT_SOURCE_DIR}/src/x86/intel_galileo_rev_g.c
${PROJECT_SOURCE_DIR}/src/x86/intel_edison_fab_c.c
${PROJECT_SOURCE_DIR}/src/x86/intel_de3815.c
${PROJECT_SOURCE_DIR}/src/x86/intel_minnow_max.c
PARENT_SCOPE
)

148
src/x86/intel_de3815.c Normal file
View File

@@ -0,0 +1,148 @@
/*
* Author: Thomas Ingleby <thomas.c.ingleby@intel.com>
* Copyright (c) 2014 Intel Corporation.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <stdlib.h>
#include <string.h>
#include "common.h"
#include "intel_de3815.h"
#define PLATFORM_NAME "Intel DE3815"
#define MAX_SIZE 64
#define SYSFS_CLASS_GPIO "/sys/class/gpio"
mraa_board_t*
mraa_intel_de3815()
{
mraa_board_t* b = (mraa_board_t*) malloc(sizeof(mraa_board_t));
if (b == NULL) {
return NULL;
}
b->platform_name_length = strlen(PLATFORM_NAME) + 1;
b->platform_name = (char*) malloc(sizeof(char) * b->platform_name_length);
if (b->platform_name == NULL) {
goto error;
}
strncpy(b->platform_name, PLATFORM_NAME, b->platform_name_length);
b->phy_pin_count = 18;
//b->gpio_count = 14;
b->aio_count = 0;
b->adc_raw = 0;
b->adc_supported = 0;
b->pwm_default_period = 500;
b->pwm_max_period = 2147483;
b->pwm_min_period = 1;
b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t)*MRAA_INTEL_DE3815_PINCOUNT);
if (b->pins == NULL) {
goto error;
}
strncpy(b->pins[0].name, "1.8v", 8);
b->pins[0].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
strncpy(b->pins[1].name, "GND", 8);
b->pins[1].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
strncpy(b->pins[2].name, "HDMIcec", 8);
b->pins[2].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
strncpy(b->pins[3].name, "DMICclk", 8);
b->pins[3].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
strncpy(b->pins[4].name, "3.3v", 8);
b->pins[4].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
strncpy(b->pins[5].name, "DMICda", 8);
b->pins[5].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
strncpy(b->pins[6].name, "Key", 8);
b->pins[6].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
strncpy(b->pins[7].name, "SMB-A", 8);
b->pins[7].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
strncpy(b->pins[8].name, "5v", 8);
b->pins[8].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
strncpy(b->pins[9].name, "SCI", 8);
b->pins[9].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
strncpy(b->pins[10].name, "PWM0", 8);
b->pins[10].capabilites = (mraa_pincapabilities_t) {1,0,1,0,0,0,0,0};
b->pins[10].pwm.pinmap = 0;
b->pins[10].pwm.parent_id = 0;
b->pins[10].pwm.mux_total = 0;
strncpy(b->pins[11].name, "PWM1", 8);
b->pins[11].capabilites = (mraa_pincapabilities_t) {1,0,1,0,0,0,0,0};
b->pins[11].pwm.pinmap = 0;
b->pins[11].pwm.parent_id = 1;
b->pins[11].pwm.mux_total = 0;
strncpy(b->pins[12].name, "I2C0SCL", 8);
b->pins[12].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,1,0,0};
b->pins[12].i2c.pinmap = 1;
b->pins[12].i2c.mux_total = 0;
strncpy(b->pins[13].name, "I2C0SDA", 8);
b->pins[13].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,1,0,0};
b->pins[13].i2c.pinmap = 1;
b->pins[13].i2c.mux_total = 0;
strncpy(b->pins[14].name, "I2C1SCL", 8);
b->pins[14].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,1,0,0};
b->pins[14].i2c.pinmap = 1;
b->pins[14].i2c.mux_total = 0;
strncpy(b->pins[15].name, "I2C1SDA", 8);
b->pins[15].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,1,0,0};
b->pins[15].i2c.pinmap = 1;
b->pins[15].i2c.mux_total = 0;
strncpy(b->pins[16].name, "SMB_CLK", 8);
b->pins[16].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
strncpy(b->pins[17].name, "SMB_SDA", 8);
b->pins[17].capabilites = (mraa_pincapabilities_t) {1,0,0,0,0,0,0,0};
//BUS DEFINITIONS
b->i2c_bus_count = 2;
b->def_i2c_bus = 0;
b->i2c_bus[0].bus_id = 0;
b->i2c_bus[0].sda = 12;
b->i2c_bus[0].scl = 13;
b->i2c_bus[1].bus_id = 1;
b->i2c_bus[1].sda = 14;
b->i2c_bus[1].scl = 15;
b->spi_bus_count = 1;
b->def_spi_bus = 0;
b->spi_bus[0].bus_id = 1;
b->spi_bus[0].slave_s = 0;
b->spi_bus[0].cs = 10;
b->spi_bus[0].mosi = 11;
b->spi_bus[0].miso = 12;
b->spi_bus[0].sclk = 13;
return b;
error:
syslog(LOG_CRIT, "de3815: Platform failed to initialise");
free(b);
return NULL;
}

1398
src/x86/intel_edison_fab_c.c Normal file
View File

File diff suppressed because it is too large Load Diff

419
src/x86/intel_galileo_rev_d.c Normal file
View File

@@ -0,0 +1,419 @@
/*
* Author: Thomas Ingleby <thomas.c.ingleby@intel.com>
* Copyright (c) 2014 Intel Corporation.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <stdlib.h>
#include <string.h>
#include <sys/mman.h>
#include "common.h"
#include "intel_galileo_rev_d.h"
#define UIO_PATH "/dev/uio0"
#define PLATFORM_NAME "Intel Galileo Gen 1"
static uint8_t *mmap_reg = NULL;
static int mmap_fd = 0;
static int mmap_size = 0x1000;
static unsigned int mmap_count = 0;
static mraa_result_t
mraa_intel_galileo_g1_mmap_unsetup()
{
if (mmap_reg == NULL) {
syslog(LOG_WARNING, "galileo1: Mmap null register nothing to unsetup");
return MRAA_ERROR_INVALID_RESOURCE;
}
munmap(mmap_reg, mmap_size);
mmap_reg = NULL;
close(mmap_fd);
return MRAA_SUCCESS;
}
mraa_result_t
mraa_intel_galileo_g1_mmap_write(mraa_gpio_context dev, int value)
{
int bitpos = plat->pins[dev->phy_pin].mmap.bit_pos;
if (value) {
*((unsigned *)mmap_reg) |= (1<<bitpos);
return MRAA_SUCCESS;
}
*((unsigned *)mmap_reg) &= ~(1<<bitpos);
return MRAA_SUCCESS;
}
mraa_result_t
mraa_intel_galileo_g1_mmap_setup(mraa_gpio_context dev, mraa_boolean_t en)
{
if (dev == NULL) {
syslog(LOG_ERR, "galileo1: Gpio context not valid");
return MRAA_ERROR_INVALID_HANDLE;
}
if (mraa_pin_mode_test(dev->phy_pin, MRAA_PIN_FAST_GPIO) == 0) {
syslog(LOG_WARNING, "galileo1: Mmap not available on this pin");
return MRAA_ERROR_NO_RESOURCES;
}
if (en == 0) {
if (dev->mmap_write == NULL) {
syslog(LOG_NOTICE, "galileo1: Can't disable disabled mmap gpio");
return MRAA_ERROR_INVALID_PARAMETER;
}
dev->mmap_write = NULL;
mmap_count--;
if (mmap_count == 0) {
return mraa_intel_galileo_g1_mmap_unsetup();
}
return MRAA_SUCCESS;
}
if (dev->mmap_write != NULL) {
syslog(LOG_ERR, "galileo1: Can't enable enabled mmap gpio");
return MRAA_ERROR_INVALID_PARAMETER;
}
if (mmap_reg == NULL) {
if ((mmap_fd = open(UIO_PATH, O_RDWR)) < 0) {
syslog(LOG_ERR, "galileo1: Unable to open UIO device");
return MRAA_ERROR_INVALID_RESOURCE;
}
mmap_reg = mmap(NULL, mmap_size, PROT_READ|PROT_WRITE,
MAP_SHARED, mmap_fd, 0);
if (mmap_reg == MAP_FAILED) {
syslog(LOG_ERR, "galileo1: Mmap failed to mmap");
mmap_reg = NULL;
close(mmap_fd);
return MRAA_ERROR_NO_RESOURCES;
}
}
if (mraa_setup_mux_mapped(plat->pins[dev->phy_pin].mmap.gpio)
!= MRAA_SUCCESS) {
syslog(LOG_ERR, "galileo1: Unable to setup required multiplexers for mmap");
return MRAA_ERROR_INVALID_RESOURCE;
}
dev->mmap_write = &mraa_intel_galileo_g1_mmap_write;
return MRAA_SUCCESS;
}
mraa_board_t*
mraa_intel_galileo_rev_d()
{
mraa_board_t* b = (mraa_board_t*) malloc(sizeof(mraa_board_t));
if (b == NULL) {
return NULL;
}
b->platform_name_length = strlen(PLATFORM_NAME) + 1;
b->platform_name = (char*) malloc(sizeof(char) * b->platform_name_length);
if (b->platform_name == NULL) {
goto error;
}
strncpy(b->platform_name, PLATFORM_NAME, b->platform_name_length);
b->phy_pin_count = 20;
b->gpio_count = 14;
b->aio_count = 6;
b->uart_dev_count = 2;
b->adc_raw = 12;
b->adc_supported = 10;
b->pwm_default_period = 500;
b->pwm_max_period = 7968;
b->pwm_min_period = 1;
advance_func->gpio_mmap_setup = &mraa_intel_galileo_g1_mmap_setup;
b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t)*MRAA_INTEL_GALILEO_REV_D_PINCOUNT);
if (b->pins == NULL) {
goto error;
}
//GPIO IO0 - IO10
strncpy(b->pins[0].name, "IO0", 8);
b->pins[0].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,1};
b->pins[0].gpio.pinmap = 50;
b->pins[0].gpio.parent_id = 0;
b->pins[0].gpio.mux_total = 1;
b->pins[0].gpio.mux[0].pin = 40;
b->pins[0].gpio.mux[0].value = 1;
b->pins[0].uart.pinmap = 0;
b->pins[0].uart.parent_id = 0;
b->pins[0].uart.mux_total = 1;
b->pins[0].uart.mux[0].pin = 40;
b->pins[0].uart.mux[0].value = 0;
strncpy(b->pins[1].name, "IO1", 8);
b->pins[1].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,1};
b->pins[1].gpio.pinmap = 51;
b->pins[1].gpio.mux_total = 1;
b->pins[1].gpio.mux[0].pin = 41;
b->pins[1].gpio.mux[0].value = 1;
b->pins[1].uart.pinmap = 0;
b->pins[1].uart.parent_id = 0;
b->pins[1].uart.mux_total = 1;
b->pins[1].uart.mux[0].pin = 41;
b->pins[1].uart.mux[0].value = 0;
strncpy(b->pins[2].name, "IO2", 8);
b->pins[2].capabilites = (mraa_pincapabilities_t) {1,1,0,1,0,0,0,0};
b->pins[2].gpio.pinmap = 32;
b->pins[2].gpio.mux_total = 1;
b->pins[2].gpio.mux[0].pin = 31;
b->pins[2].gpio.mux[0].value = 1;
b->pins[2].mmap.gpio.pinmap = 14;
strncpy(b->pins[2].mmap.mem_dev, "/dev/uio0", 12);
b->pins[2].mmap.gpio.mux_total = 2;
b->pins[2].mmap.gpio.mux[0].pin = 31;
b->pins[2].mmap.gpio.mux[0].value = 0;
b->pins[2].mmap.gpio.mux[1].pin = 14;
b->pins[2].mmap.gpio.mux[1].value = 0;
b->pins[2].mmap.mem_sz = 0x1000;
b->pins[2].mmap.bit_pos = 6;
strncpy(b->pins[3].name, "IO3", 8);
b->pins[3].capabilites = (mraa_pincapabilities_t) {1,1,1,1,0,0,0,0};
b->pins[3].gpio.pinmap = 18;
b->pins[3].gpio.mux_total = 1;
b->pins[3].gpio.mux[0].pin = 30;
b->pins[3].gpio.mux[0].value = 1;
b->pins[3].mmap.gpio.pinmap = 15;
strncpy(b->pins[3].mmap.mem_dev, "/dev/uio0", 12);
b->pins[3].mmap.gpio.mux_total = 2;
b->pins[3].mmap.gpio.mux[0].pin = 30;
b->pins[3].mmap.gpio.mux[0].value = 0;
b->pins[3].mmap.gpio.mux[1].pin = 15;
b->pins[3].mmap.gpio.mux[1].value = 0;
b->pins[3].mmap.mem_sz = 0x1000;
b->pins[3].mmap.bit_pos = 7;
b->pins[3].pwm.pinmap = 3;
b->pins[3].pwm.parent_id = 0;
b->pins[3].pwm.mux_total = 1;
b->pins[3].pwm.mux[0].pin = 30;
b->pins[3].pwm.mux[0].value = 1;
strncpy(b->pins[4].name, "IO4", 8);
b->pins[4].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
b->pins[4].gpio.pinmap = 28;
b->pins[4].gpio.mux_total = 0;
strncpy(b->pins[5].name, "IO5", 8);
b->pins[5].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
b->pins[5].gpio.pinmap = 17;
b->pins[5].gpio.mux_total = 0;
b->pins[5].pwm.pinmap = 5;
b->pins[5].pwm.parent_id = 0;
b->pins[5].pwm.mux_total = 0;
strncpy(b->pins[6].name, "IO6", 8);
b->pins[6].gpio.pinmap = 24;
b->pins[6].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
b->pins[6].gpio.mux_total = 0;
b->pins[6].pwm.pinmap = 6;
b->pins[6].pwm.parent_id = 0;
b->pins[6].pwm.mux_total = 0;
strncpy(b->pins[7].name, "IO7", 8);
b->pins[7].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
b->pins[7].gpio.pinmap = 27;
b->pins[7].gpio.mux_total = 0;
strncpy(b->pins[8].name, "IO8", 8);
b->pins[8].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
b->pins[8].gpio.pinmap = 26;
b->pins[8].gpio.mux_total = 0;
strncpy(b->pins[9].name, "IO9", 8);
b->pins[9].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
b->pins[9].gpio.pinmap = 19;
b->pins[9].gpio.mux_total = 0;
b->pins[9].pwm.pinmap = 1;
b->pins[9].pwm.parent_id = 0;
b->pins[9].pwm.mux_total = 0;
strncpy(b->pins[10].name, "IO10", 8);
b->pins[10].capabilites = (mraa_pincapabilities_t) {1,1,1,0,1,0,0,0};
b->pins[10].gpio.pinmap = 16;
b->pins[10].gpio.mux_total = 1;
b->pins[10].gpio.mux[0].pin = 42;
b->pins[10].gpio.mux[0].value = 1;
b->pins[10].pwm.pinmap = 7;
b->pins[10].pwm.parent_id = 0;
b->pins[10].pwm.mux_total = 1;
b->pins[10].pwm.mux[0].pin = 42;
b->pins[10].pwm.mux[0].value = 1;
b->pins[10].spi.pinmap = 1;
b->pins[10].spi.mux_total = 1;
b->pins[10].spi.mux[0].pin = 42;
b->pins[10].spi.mux[0].value = 0;
strncpy(b->pins[11].name, "IO11", 8);
b->pins[11].capabilites = (mraa_pincapabilities_t) {1,1,1,0,1,0,0,0};
b->pins[11].gpio.pinmap = 25;
b->pins[11].gpio.mux_total = 1;
b->pins[11].gpio.mux[0].pin = 43;
b->pins[11].gpio.mux[0].value = 1;
b->pins[11].pwm.pinmap = 4;
b->pins[11].pwm.parent_id = 0;
b->pins[11].pwm.mux_total = 1;
b->pins[11].pwm.mux[0].pin = 43;
b->pins[11].pwm.mux[0].value = 1;
b->pins[11].spi.pinmap = 1;
b->pins[11].spi.mux_total = 1;
b->pins[11].spi.mux[0].pin = 43;
b->pins[11].spi.mux[0].value = 0;
strncpy(b->pins[12].name, "IO12", 8);
b->pins[12].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
b->pins[12].gpio.pinmap = 38;
b->pins[12].gpio.mux_total = 1;
b->pins[12].gpio.mux[0].pin = 54;
b->pins[12].gpio.mux[0].value = 1;
b->pins[12].spi.pinmap = 1;
b->pins[12].spi.mux_total = 1;
b->pins[12].spi.mux[0].pin = 54;
b->pins[12].spi.mux[0].value = 0;
strncpy(b->pins[13].name, "IO13", 8);
b->pins[13].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
b->pins[13].gpio.pinmap = 39;
b->pins[13].gpio.mux_total = 1;
b->pins[13].gpio.mux[0].pin = 55;
b->pins[13].gpio.mux[0].value = 1;
b->pins[13].spi.pinmap = 1;
b->pins[13].spi.mux_total = 1;
b->pins[13].spi.mux[0].pin = 55;
b->pins[13].spi.mux[0].value = 0;
strncpy(b->pins[14].name, "A0", 8);
b->pins[14].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
b->pins[14].gpio.pinmap = 44;
b->pins[14].gpio.mux_total = 1;
b->pins[14].gpio.mux[0].pin = 37;
b->pins[14].gpio.mux[0].value = 1;
b->pins[14].aio.pinmap = 0;
b->pins[14].aio.mux_total = 1;
b->pins[14].aio.mux[0].pin = 37;
b->pins[14].aio.mux[0].value = 0;
strncpy(b->pins[15].name, "A1", 8);
b->pins[15].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
b->pins[15].gpio.pinmap = 45;
b->pins[15].gpio.mux_total = 1;
b->pins[15].gpio.mux[0].pin = 36;
b->pins[15].gpio.mux[0].value = 1;
b->pins[15].aio.pinmap = 1;
b->pins[15].aio.mux_total = 1;
b->pins[15].aio.mux[0].pin = 36;
b->pins[15].aio.mux[0].value = 0;
strncpy(b->pins[16].name, "A2", 8);
b->pins[16].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
b->pins[16].gpio.pinmap = 46;
b->pins[16].gpio.mux_total = 1;
b->pins[16].gpio.mux[0].pin = 23;
b->pins[16].gpio.mux[0].value = 1;
b->pins[16].aio.pinmap = 2;
b->pins[16].aio.mux_total = 1;
b->pins[16].aio.mux[0].pin = 23;
b->pins[16].aio.mux[0].value = 0;
strncpy(b->pins[17].name, "A3", 8);
b->pins[17].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
b->pins[17].gpio.pinmap = 47;
b->pins[17].gpio.mux_total = 1;
b->pins[17].gpio.mux[0].pin = 22;
b->pins[17].gpio.mux[0].value = 1;
b->pins[17].aio.pinmap = 3;
b->pins[17].aio.mux_total = 1;
b->pins[17].aio.mux[0].pin = 22;
b->pins[17].aio.mux[0].value = 0;
strncpy(b->pins[18].name, "A4", 8);
b->pins[18].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,1,0};
b->pins[18].gpio.pinmap = 48;
b->pins[18].gpio.mux_total = 2;
b->pins[18].gpio.mux[0].pin = 29;
b->pins[18].gpio.mux[0].value = 1;
b->pins[18].gpio.mux[1].pin = 21;
b->pins[18].gpio.mux[1].value = 1;
b->pins[18].i2c.pinmap = 1;
b->pins[18].i2c.mux_total = 1;
b->pins[18].i2c.mux[0].pin = 29;
b->pins[18].i2c.mux[0].value = 0;
b->pins[18].aio.pinmap = 4;
b->pins[18].aio.mux_total = 2;
b->pins[18].aio.mux[0].pin = 29;
b->pins[18].aio.mux[0].value = 1;
b->pins[18].aio.mux[1].pin = 21;
b->pins[18].aio.mux[1].value = 0;
strncpy(b->pins[19].name, "A5", 8);
b->pins[19].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,1,0};
b->pins[19].gpio.pinmap = 49;
b->pins[19].gpio.mux_total = 2;
b->pins[19].gpio.mux[0].pin = 29;
b->pins[19].gpio.mux[0].value = 1;
b->pins[19].gpio.mux[1].pin = 20;
b->pins[19].gpio.mux[1].value = 1;
b->pins[19].i2c.pinmap = 1;
b->pins[19].i2c.mux_total = 1;
b->pins[19].i2c.mux[0].pin = 29;
b->pins[19].i2c.mux[0].value = 0;
b->pins[19].aio.pinmap = 5;
b->pins[19].aio.mux_total = 2;
b->pins[19].aio.mux[0].pin = 29;
b->pins[19].aio.mux[0].value = 1;
b->pins[19].aio.mux[1].pin = 20;
b->pins[19].aio.mux[1].value = 0;
//BUS DEFINITIONS
b->i2c_bus_count = 1;
b->def_i2c_bus = 0;
b->i2c_bus[0].bus_id = 0;
b->i2c_bus[0].sda = 18;
b->i2c_bus[0].scl = 19;
b->spi_bus_count = 1;
b->def_spi_bus = 0;
b->spi_bus[0].bus_id = 1;
b->spi_bus[0].slave_s = 0;
b->spi_bus[0].cs = 10;
b->spi_bus[0].mosi = 11;
b->spi_bus[0].miso = 12;
b->spi_bus[0].sclk = 13;
b->def_uart_dev = 0;
b->uart_dev[0].rx = 0;
b->uart_dev[0].tx = 1;
b->uart_dev[1].rx = -1;
b->uart_dev[1].tx = -1;
return b;
error:
syslog(LOG_CRIT, "galileo1: Platform failed to initialise");
free(b);
return NULL;
}

741
src/x86/intel_galileo_rev_g.c Normal file
View File

@@ -0,0 +1,741 @@
/*
* Author: Brendan Le Foll <brendan.le.foll@intel.com>
* Author: Thomas Ingleby <thomas.c.ingleby@intel.com>
* Copyright (c) 2014 Intel Corporation.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <stdlib.h>
#include <string.h>
#include <sys/mman.h>
#include "common.h"
#include "intel_galileo_rev_g.h"
#define MAX_SIZE 64
#define SYSFS_CLASS_GPIO "/sys/class/gpio"
#define PLATFORM_NAME "Intel Galileo Gen 2"
#define UIO_PATH "/dev/uio0"
static uint8_t *mmap_reg = NULL;
static int mmap_fd = 0;
static int mmap_size = 0x1000;
static unsigned int mmap_count = 0;
static unsigned int pullup_map[] = {33,29,35,17,37,19,21,39,41,23,27,25,43,31,49,51,53,55,57,59};
mraa_result_t
mraa_intel_galileo_gen2_dir_pre(mraa_gpio_context dev, gpio_dir_t dir)
{
if (dev->phy_pin >= 0) {
int pin = dev->phy_pin;
if (plat->pins[pin].gpio.complex_cap.complex_pin != 1)
return MRAA_SUCCESS;
if (plat->pins[pin].gpio.complex_cap.output_en == 1) {
mraa_gpio_context output_e = mraa_gpio_init_raw(plat->pins[pin].gpio.output_enable);
if (output_e == NULL) {
return MRAA_ERROR_INVALID_RESOURCE;
}
if (mraa_gpio_dir(output_e, MRAA_GPIO_OUT) != MRAA_SUCCESS) {
return mraa_gpio_close(output_e);
}
int output_val = 1;
if (dir == MRAA_GPIO_OUT) {
output_val = 0;
}
if (mraa_gpio_write(output_e, output_val) != MRAA_SUCCESS) {
return mraa_gpio_close(output_e);
}
mraa_gpio_close(output_e);
}
}
return MRAA_SUCCESS;
}
mraa_result_t
mraa_intel_galileo_gen2_i2c_init_pre(unsigned int bus)
{
mraa_gpio_context io18 = mraa_gpio_init_raw(57);
int status = 0;
if (io18 == NULL) {
return MRAA_ERROR_UNSPECIFIED;
}
status += mraa_gpio_dir(io18, MRAA_GPIO_IN);
status += mraa_gpio_mode(io18, MRAA_GPIO_HIZ);
mraa_gpio_close(io18);
mraa_gpio_context io19 = mraa_gpio_init_raw(59);
if (io19 == NULL) {
return MRAA_ERROR_UNSPECIFIED;
}
status += mraa_gpio_dir(io19, MRAA_GPIO_IN);
status += mraa_gpio_mode(io19, MRAA_GPIO_HIZ);
mraa_gpio_close(io19);
if (status > 0) {
return MRAA_ERROR_UNSPECIFIED;
}
return MRAA_SUCCESS;
}
mraa_result_t
mraa_intel_galileo_gen2_pwm_period_replace(mraa_pwm_context dev, int period)
{
char bu[MAX_SIZE];
snprintf(bu,MAX_SIZE ,"/sys/class/pwm/pwmchip%d/device/pwm_period", dev->chipid);
int period_f = open(bu, O_RDWR);
if (period_f == -1) {
syslog(LOG_ERR, "galileo2: Failed to open period for writing!");
return MRAA_ERROR_INVALID_RESOURCE;
}
char out[MAX_SIZE];
int length = snprintf(out, MAX_SIZE, "%d", period);
if (write(period_f, out, length*sizeof(char)) == -1) {
close(period_f);
return MRAA_ERROR_INVALID_RESOURCE;
}
close(period_f);
return MRAA_SUCCESS;
}
mraa_result_t
mraa_intel_galileo_gen2_gpio_mode_replace(mraa_gpio_context dev, gpio_mode_t mode)
{
if (dev->value_fp != -1) {
close(dev->value_fp);
dev->value_fp = -1;
}
mraa_gpio_context pullup_e;
pullup_e = mraa_gpio_init_raw(pullup_map[dev->phy_pin]);
if (pullup_e == NULL) {
return MRAA_ERROR_INVALID_RESOURCE;
}
if (mraa_gpio_dir(pullup_e, MRAA_GPIO_IN) != MRAA_SUCCESS) {
mraa_gpio_close(pullup_e);
syslog(LOG_ERR, "galileo2: Failed to set gpio pullup");
return MRAA_ERROR_INVALID_RESOURCE;
}
char filepath[MAX_SIZE];
snprintf(filepath, MAX_SIZE, SYSFS_CLASS_GPIO "/gpio%d/drive", pullup_map[dev->phy_pin]);
int drive = open(filepath, O_WRONLY);
if (drive == -1) {
syslog(LOG_ERR, "galileo2: Failed to open drive for writing");
return MRAA_ERROR_INVALID_RESOURCE;
}
char bu[MAX_SIZE];
int length;
int value = -1;
switch(mode) {
case MRAA_GPIO_STRONG:
length = snprintf(bu, sizeof(bu), "hiz");
break;
case MRAA_GPIO_PULLUP:
length = snprintf(bu, sizeof(bu), "strong");
value = 1;
break;
case MRAA_GPIO_PULLDOWN:
length = snprintf(bu, sizeof(bu), "pulldown");
value = 0;
break;
case MRAA_GPIO_HIZ:
close(drive);
return MRAA_SUCCESS;
break;
default:
close(drive);
return MRAA_ERROR_FEATURE_NOT_IMPLEMENTED;
}
if (write(drive, bu, length*sizeof(char)) == -1) {
syslog(LOG_ERR, "galileo2: Failed to write to drive mode");
close(drive);
mraa_gpio_close(pullup_e);
return MRAA_ERROR_INVALID_RESOURCE;
}
if (value != -1) {
mraa_result_t ret = mraa_gpio_dir(pullup_e, MRAA_GPIO_OUT);
ret += mraa_gpio_write(pullup_e, value);
if (ret != MRAA_SUCCESS) {
syslog(LOG_ERR, "galileo2: Error Setting pullup");
close(drive);
return MRAA_ERROR_INVALID_RESOURCE;
}
}
mraa_gpio_close(pullup_e);
close(drive);
return MRAA_SUCCESS;
}
mraa_result_t
mraa_intel_galileo_gen2_uart_init_pre(int index)
{
mraa_gpio_context io0_output = mraa_gpio_init_raw(32);
if (io0_output == NULL) {
return MRAA_ERROR_INVALID_RESOURCE;
}
mraa_gpio_context io1_output = mraa_gpio_init_raw(28);
if (io1_output == NULL) {
mraa_gpio_close(io0_output);
return MRAA_ERROR_INVALID_RESOURCE;
}
int status = 0;
status += mraa_gpio_dir(io0_output, MRAA_GPIO_OUT);
status += mraa_gpio_dir(io1_output, MRAA_GPIO_OUT);
status += mraa_gpio_write(io0_output, 1);
status += mraa_gpio_write(io1_output, 0);
mraa_gpio_close(io0_output);
mraa_gpio_close(io1_output);
if (status > 0) {
return MRAA_ERROR_UNSPECIFIED;
}
return MRAA_SUCCESS;
}
static mraa_result_t
mraa_intel_galileo_g2_mmap_unsetup()
{
if (mmap_reg == NULL) {
syslog(LOG_ERR, "mmap: null register cant unsetup");
return MRAA_ERROR_INVALID_RESOURCE;
}
munmap(mmap_reg, mmap_size);
mmap_reg = NULL;
close(mmap_fd);
return MRAA_SUCCESS;
}
mraa_result_t
mraa_intel_galileo_g2_mmap_write(mraa_gpio_context dev, int value)
{
int bitpos = plat->pins[dev->phy_pin].mmap.bit_pos;
if (value) {
*((unsigned *)mmap_reg) |= (1<<bitpos);
return MRAA_SUCCESS;
}
*((unsigned *)mmap_reg) &= ~(1<<bitpos);
return MRAA_SUCCESS;
}
mraa_result_t
mraa_intel_galileo_g2_mmap_setup(mraa_gpio_context dev, mraa_boolean_t en)
{
if (dev == NULL) {
syslog(LOG_ERR, "Galileo mmap: context not valid");
return MRAA_ERROR_INVALID_HANDLE;
}
if (mraa_pin_mode_test(dev->phy_pin, MRAA_PIN_FAST_GPIO) == 0) {
syslog(LOG_ERR, "Galileo mmap: mmap not on this pin");
return MRAA_ERROR_NO_RESOURCES;
}
if (en == 0) {
if (dev->mmap_write == NULL) {
syslog(LOG_ERR, "mmap: can't disable disabled mmap gpio");
return MRAA_ERROR_INVALID_PARAMETER;
}
dev->mmap_write = NULL;
mmap_count--;
if (mmap_count == 0) {
return mraa_intel_galileo_g2_mmap_unsetup();
}
return MRAA_SUCCESS;
}
if (dev->mmap_write != NULL) {
syslog(LOG_ERR, "mmap: can't enable enabled mmap gpio");
return MRAA_ERROR_INVALID_PARAMETER;
}
if (mmap_reg == NULL) {
if ((mmap_fd = open(UIO_PATH, O_RDWR)) < 0) {
syslog(LOG_ERR, "mmap: Unable to open UIO device");
return MRAA_ERROR_INVALID_RESOURCE;
}
mmap_reg = mmap(NULL, mmap_size, PROT_READ|PROT_WRITE,
MAP_SHARED, mmap_fd, 0);
if (mmap_reg == MAP_FAILED) {
syslog(LOG_ERR, "mmap: failed to mmap");
mmap_reg = NULL;
close(mmap_fd);
return MRAA_ERROR_NO_RESOURCES;
}
}
if (mraa_setup_mux_mapped(plat->pins[dev->phy_pin].mmap.gpio)
!= MRAA_SUCCESS) {
syslog(LOG_ERR, "mmap: unable to setup required multiplexers");
return MRAA_ERROR_INVALID_RESOURCE;
}
dev->mmap_write = &mraa_intel_galileo_g2_mmap_write;
return MRAA_SUCCESS;
}
mraa_board_t*
mraa_intel_galileo_gen2()
{
mraa_board_t* b = (mraa_board_t*) malloc(sizeof(mraa_board_t));
if (b == NULL) {
return NULL;
}
b->platform_name_length = strlen(PLATFORM_NAME) + 1;
b->platform_name = (char*) malloc(sizeof(char) * b->platform_name_length);
if (b->platform_name == NULL) {
goto error;
}
strncpy(b->platform_name, PLATFORM_NAME, b->platform_name_length);
b->phy_pin_count = 20;
b->gpio_count = 14;
b->aio_count = 6;
b->adc_raw = 12;
b->adc_supported = 10;
b->pwm_default_period = 5000;
b->pwm_max_period = 41666;
b->pwm_min_period = 666;
advance_func->gpio_dir_pre = &mraa_intel_galileo_gen2_dir_pre;
advance_func->i2c_init_pre = &mraa_intel_galileo_gen2_i2c_init_pre;
advance_func->pwm_period_replace = &mraa_intel_galileo_gen2_pwm_period_replace;
advance_func->gpio_mode_replace = &mraa_intel_galileo_gen2_gpio_mode_replace;
advance_func->uart_init_pre = &mraa_intel_galileo_gen2_uart_init_pre;
advance_func->gpio_mmap_setup = &mraa_intel_galileo_g2_mmap_setup;
b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t)*MRAA_INTEL_GALILEO_GEN_2_PINCOUNT);
if (b->pins == NULL) {
goto error;
}
strncpy(b->pins[0].name, "IO0", 8);
b->pins[0].capabilites = (mraa_pincapabilities_t) {1,1,0,1,0,0,0,1};
b->pins[0].gpio.pinmap = 11;
b->pins[0].gpio.parent_id = 0;
b->pins[0].gpio.mux_total = 0;
b->pins[0].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
b->pins[0].gpio.output_enable = 32;
b->pins[0].gpio.pullup_enable = 33;
b->pins[0].mmap.gpio.pinmap = 11;
strncpy(b->pins[0].mmap.mem_dev, "/dev/uio0", 12);
b->pins[0].mmap.gpio.mux_total = 2;
b->pins[0].mmap.gpio.mux[0].pin = 32;
b->pins[0].mmap.gpio.mux[0].value = 0;
b->pins[0].mmap.gpio.mux[1].pin = 11;
b->pins[0].mmap.gpio.mux[1].value = 0;
b->pins[0].mmap.mem_sz = 0x1000;
b->pins[0].mmap.bit_pos = 3;
b->pins[0].uart.parent_id = 0;
b->pins[0].uart.mux_total = 0;
strncpy(b->pins[1].name, "IO1", 8);
b->pins[1].capabilites = (mraa_pincapabilities_t) {1,1,0,1,0,0,0,1};
b->pins[1].gpio.pinmap = 12;
b->pins[1].gpio.parent_id = 0;
b->pins[1].gpio.mux_total = 1;
b->pins[1].gpio.mux[0].pin = 45;
b->pins[1].gpio.mux[0].value = 0;
b->pins[1].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
b->pins[1].gpio.output_enable = 28;
b->pins[1].gpio.pullup_enable = 29;
b->pins[1].mmap.gpio.pinmap = 12;
strncpy(b->pins[1].mmap.mem_dev, "/dev/uio0", 12);
b->pins[1].mmap.gpio.mux_total = 3;
b->pins[1].mmap.gpio.mux[0].pin = 45;
b->pins[1].mmap.gpio.mux[0].value = 0;
b->pins[1].mmap.gpio.mux[1].pin = 28;
b->pins[1].mmap.gpio.mux[1].value = 0;
b->pins[1].mmap.gpio.mux[2].pin = 12;
b->pins[1].mmap.gpio.mux[2].value = 0;
b->pins[1].mmap.mem_sz = 0x1000;
b->pins[1].mmap.bit_pos = 4;
b->pins[1].uart.parent_id = 0;
b->pins[1].uart.mux_total = 1;
b->pins[1].uart.mux[0].pin = 45;
b->pins[1].uart.mux[0].value = 1;
strncpy(b->pins[2].name, "IO2", 8);
b->pins[2].capabilites = (mraa_pincapabilities_t) {1,1,0,1,0,0,0};
b->pins[2].gpio.pinmap = 13;
b->pins[2].gpio.parent_id = 0;
b->pins[2].gpio.mux_total = 1;
b->pins[2].gpio.mux[0].pin = 77;
b->pins[2].gpio.mux[0].value = 0;
b->pins[2].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
b->pins[2].gpio.output_enable = 34;
b->pins[2].gpio.pullup_enable = 35;
b->pins[2].mmap.gpio.pinmap = 13;
strncpy(b->pins[2].mmap.mem_dev, "/dev/uio0", 12);
b->pins[2].mmap.gpio.mux_total = 3;
b->pins[2].mmap.gpio.mux[0].pin = 77;
b->pins[2].mmap.gpio.mux[0].value = 0;
b->pins[2].mmap.gpio.mux[1].pin = 34;
b->pins[2].mmap.gpio.mux[1].value = 0;
b->pins[2].mmap.gpio.mux[2].pin = 13;
b->pins[2].mmap.gpio.mux[2].value = 0;
b->pins[2].mmap.mem_sz = 0x1000;
b->pins[2].mmap.bit_pos = 5;
strncpy(b->pins[3].name, "IO3", 8);
b->pins[3].capabilites = (mraa_pincapabilities_t) {1,1,1,1,0,0,0};
b->pins[3].gpio.pinmap = 14;
b->pins[3].gpio.parent_id = 0;
b->pins[3].gpio.mux_total = 2;
b->pins[3].gpio.mux[0].pin = 76;
b->pins[3].gpio.mux[0].value = 0;
b->pins[3].gpio.mux[1].pin = 64;
b->pins[3].gpio.mux[1].value = 0;
b->pins[3].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
b->pins[3].gpio.output_enable = 16;
b->pins[3].gpio.pullup_enable = 17;
b->pins[3].pwm.pinmap = 1;
b->pins[3].pwm.parent_id = 0;
b->pins[3].pwm.mux_total = 3;
b->pins[3].pwm.mux[0].pin = 76;
b->pins[3].pwm.mux[0].value = 0;
b->pins[3].pwm.mux[1].pin = 64;
b->pins[3].pwm.mux[1].value = 1;
b->pins[3].pwm.mux[2].pin = 16;
b->pins[3].pwm.mux[2].value = 0;
b->pins[3].mmap.gpio.pinmap = 14;
strncpy(b->pins[3].mmap.mem_dev, "/dev/uio0", 12);
b->pins[3].mmap.gpio.mux_total = 4;
b->pins[3].mmap.gpio.mux[0].pin = 76;
b->pins[3].mmap.gpio.mux[0].value = 0;
b->pins[3].mmap.gpio.mux[1].pin = 64;
b->pins[3].mmap.gpio.mux[1].value = 0;
b->pins[3].mmap.gpio.mux[2].pin = 16;
b->pins[3].mmap.gpio.mux[2].value = 0;
b->pins[3].mmap.gpio.mux[3].pin = 14;
b->pins[3].mmap.gpio.mux[3].value = 0;
b->pins[3].mmap.mem_sz = 0x1000;
b->pins[3].mmap.bit_pos = 6;
strncpy(b->pins[4].name, "IO4", 8);
b->pins[4].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
b->pins[4].gpio.pinmap = 6;
b->pins[4].gpio.parent_id = 0;
b->pins[4].gpio.mux_total = 0;
b->pins[4].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
b->pins[4].gpio.output_enable = 36;
b->pins[4].gpio.pullup_enable = 37;
strncpy(b->pins[5].name, "IO5", 8);
b->pins[5].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
b->pins[5].gpio.pinmap = 0;
b->pins[5].gpio.parent_id = 0;
b->pins[5].gpio.mux_total = 1;
b->pins[5].gpio.mux[0].pin = 66;
b->pins[5].gpio.mux[0].value = 0;
b->pins[5].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
b->pins[5].gpio.output_enable = 18;
b->pins[5].gpio.pullup_enable = 19;
b->pins[5].pwm.pinmap = 3;
b->pins[5].pwm.parent_id = 0;
b->pins[5].pwm.mux_total = 2;
b->pins[5].pwm.mux[0].pin = 66;
b->pins[5].pwm.mux[0].value = 1;
b->pins[5].pwm.mux[1].pin = 18;
b->pins[5].pwm.mux[1].value = 0;
strncpy(b->pins[6].name, "IO6", 8);
b->pins[6].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
b->pins[6].gpio.pinmap = 1;
b->pins[6].gpio.parent_id = 0;
b->pins[6].gpio.mux_total = 1;
b->pins[6].gpio.mux[0].pin = 68;
b->pins[6].gpio.mux[0].value = 0;
b->pins[6].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
b->pins[6].gpio.output_enable = 20;
b->pins[6].gpio.pullup_enable = 21;
b->pins[6].pwm.pinmap = 5;
b->pins[6].pwm.parent_id = 0;
b->pins[6].pwm.mux_total = 2;
b->pins[6].pwm.mux[0].pin = 68;
b->pins[6].pwm.mux[0].value = 1;
b->pins[6].pwm.mux[1].pin = 20;
b->pins[6].pwm.mux[1].value = 0;
strncpy(b->pins[7].name, "IO7", 8);
b->pins[7].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
b->pins[7].gpio.pinmap = 38;
b->pins[7].gpio.parent_id = 0;
b->pins[7].gpio.mux_total = 0;
b->pins[7].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
b->pins[7].gpio.pullup_enable = 39;
strncpy(b->pins[8].name, "IO8", 8);
b->pins[8].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0};
b->pins[8].gpio.pinmap = 40;
b->pins[8].gpio.parent_id = 0;
b->pins[8].gpio.mux_total = 0;
b->pins[8].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
b->pins[8].gpio.pullup_enable = 41;
strncpy(b->pins[9].name, "IO9", 8);
b->pins[9].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0};
b->pins[9].gpio.pinmap = 4;
b->pins[9].gpio.parent_id = 0;
b->pins[9].gpio.mux_total = 1;
b->pins[9].gpio.mux[0].pin = 70;
b->pins[9].gpio.mux[0].value = 0;
b->pins[9].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
b->pins[9].gpio.output_enable = 22;
b->pins[9].gpio.pullup_enable = 23;
b->pins[9].pwm.pinmap = 7;
b->pins[9].pwm.parent_id = 0;
b->pins[9].pwm.mux_total = 2;
b->pins[9].pwm.mux[0].pin = 70;
b->pins[9].pwm.mux[0].value = 1;
b->pins[9].pwm.mux[1].pin = 22;
b->pins[9].pwm.mux[1].value = 0;
strncpy(b->pins[10].name, "IO10", 8);
b->pins[10].capabilites = (mraa_pincapabilities_t) {1,1,1,1,1,0,0};
b->pins[10].gpio.pinmap = 10;
b->pins[10].gpio.parent_id = 0;
b->pins[10].gpio.mux_total = 1;
b->pins[10].gpio.mux[0].pin = 74;
b->pins[10].gpio.mux[0].value = 0;
b->pins[10].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
b->pins[10].gpio.output_enable = 26;
b->pins[10].gpio.pullup_enable = 27;
b->pins[10].pwm.pinmap = 11;
b->pins[10].pwm.parent_id = 0;
b->pins[10].pwm.mux_total = 2;
b->pins[10].pwm.mux[0].pin = 74;
b->pins[10].pwm.mux[0].value = 1;
b->pins[10].pwm.mux[1].pin = 26;
b->pins[10].pwm.mux[1].value = 0;
b->pins[10].mmap.gpio.pinmap = 10;
strncpy(b->pins[10].mmap.mem_dev, "/dev/uio0", 12);
b->pins[10].mmap.gpio.mux_total = 3;
b->pins[10].mmap.gpio.mux[0].pin = 74;
b->pins[10].mmap.gpio.mux[0].value = 0;
b->pins[10].mmap.gpio.mux[1].pin = 26;
b->pins[10].mmap.gpio.mux[1].value = 0;
b->pins[10].mmap.gpio.mux[2].pin = 10;
b->pins[10].mmap.gpio.mux[2].value = 0;
b->pins[10].mmap.mem_sz = 0x1000;
b->pins[10].mmap.bit_pos = 2;
b->pins[10].spi.parent_id = 1;
b->pins[10].spi.mux_total = 1;
b->pins[10].spi.mux[0].pin = 74;
b->pins[10].spi.mux[0].value = 0;
strncpy(b->pins[11].name, "IO11", 8);
b->pins[11].capabilites = (mraa_pincapabilities_t) {1,1,1,0,1,0,0};
b->pins[11].gpio.pinmap = 5;
b->pins[11].gpio.parent_id = 0;
b->pins[11].gpio.mux_total = 2;
b->pins[11].gpio.mux[0].pin = 72;
b->pins[11].gpio.mux[0].value = 0;
b->pins[11].gpio.mux[1].pin = 44;
b->pins[11].gpio.mux[1].value = 0;
b->pins[11].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
b->pins[11].gpio.output_enable = 24;
b->pins[11].gpio.pullup_enable = 25;
b->pins[11].pwm.pinmap = 9;
b->pins[11].pwm.parent_id = 0;
b->pins[11].pwm.mux_total = 3;
b->pins[11].pwm.mux[0].pin = 72;
b->pins[11].pwm.mux[0].value = 1;
b->pins[11].pwm.mux[1].pin = 44;
b->pins[11].pwm.mux[1].value = 0;
b->pins[11].pwm.mux[2].pin = 24;
b->pins[11].pwm.mux[2].value = 0;
b->pins[11].spi.pinmap = 1;
b->pins[11].spi.mux_total = 3;
b->pins[11].spi.mux[0].pin = 72;
b->pins[11].spi.mux[0].value = 0;
b->pins[11].spi.mux[1].pin = 44;
b->pins[11].spi.mux[2].value = 1;
b->pins[11].pwm.mux[2].pin = 24;
b->pins[11].pwm.mux[2].value = 0;
strncpy(b->pins[12].name, "IO12", 8);
b->pins[12].capabilites = (mraa_pincapabilities_t) {1,1,0,1,1,0,0};
b->pins[12].gpio.pinmap = 15;
b->pins[12].gpio.parent_id = 0;
b->pins[12].gpio.mux_total = 0;
b->pins[12].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
b->pins[12].gpio.output_enable = 42;
b->pins[12].gpio.pullup_enable = 43;
b->pins[12].spi.pinmap = 1;
b->pins[12].spi.mux_total = 1;
b->pins[12].spi.mux[0].pin = 42;
b->pins[12].spi.mux[0].value = 1;
b->pins[12].mmap.gpio.pinmap = 15;
strncpy(b->pins[12].mmap.mem_dev, "/dev/uio0", 12);
b->pins[12].mmap.gpio.mux_total = 2;
b->pins[12].mmap.gpio.mux[0].pin = 42;
b->pins[12].mmap.gpio.mux[0].value = 0;
b->pins[12].mmap.gpio.mux[1].pin = 15;
b->pins[12].mmap.gpio.mux[1].value = 0;
b->pins[12].mmap.mem_sz = 0x1000;
b->pins[12].mmap.bit_pos = 7;
strncpy(b->pins[13].name, "IO13", 8);
b->pins[13].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0};
b->pins[13].gpio.pinmap = 7;
b->pins[13].gpio.parent_id = 0;
b->pins[13].gpio.mux_total = 1;
b->pins[13].gpio.mux[0].pin = 46;
b->pins[13].gpio.mux[0].value = 0;
b->pins[13].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,1,0,1,1};
b->pins[13].gpio.output_enable = 30;
b->pins[13].gpio.pullup_enable = 31;
b->pins[13].spi.pinmap = 1;
b->pins[13].spi.mux_total = 2;
b->pins[13].spi.mux[0].pin = 46;
b->pins[13].spi.mux[0].value = 1;
b->pins[13].spi.mux[1].pin = 30;
b->pins[13].spi.mux[1].value = 0;
//ANALOG
strncpy(b->pins[14].name, "A0", 8);
b->pins[14].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1};
b->pins[14].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
b->pins[14].gpio.pullup_enable = 49;
b->pins[14].aio.pinmap = 0;
b->pins[14].aio.mux_total = 1;
b->pins[14].aio.mux[0].pin = 49;
b->pins[14].aio.mux[0].value = 1;
b->pins[14].gpio.pinmap = 48;
b->pins[14].gpio.mux_total = 0;
strncpy(b->pins[15].name, "A1", 8);
b->pins[15].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1};
b->pins[15].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
b->pins[15].gpio.pullup_enable = 51;
b->pins[15].aio.pinmap = 1;
b->pins[15].aio.mux[0].pin = 51;
b->pins[15].aio.mux[0].value = 1;
b->pins[15].aio.mux_total = 0;
b->pins[15].gpio.pinmap = 50;
b->pins[15].gpio.mux_total = 0;
strncpy(b->pins[16].name, "A2", 8);
b->pins[16].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1};
b->pins[16].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
b->pins[16].gpio.pullup_enable = 53;
b->pins[16].aio.pinmap = 2;
b->pins[16].aio.mux_total = 1;
b->pins[16].aio.mux[0].pin = 53;
b->pins[16].aio.mux[0].value = 1;
b->pins[16].gpio.pinmap = 52;
b->pins[16].gpio.mux_total = 0;
strncpy(b->pins[17].name, "A3", 8);
b->pins[17].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1};
b->pins[17].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
b->pins[17].gpio.pullup_enable = 55;
b->pins[17].aio.pinmap = 3;
b->pins[17].aio.mux_total = 1;
b->pins[17].aio.mux[0].pin = 55;
b->pins[17].aio.mux[0].value = 1;
b->pins[17].gpio.pinmap = 54;
b->pins[17].gpio.mux_total = 0;
strncpy(b->pins[18].name, "A4", 8);
b->pins[18].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,1};
b->pins[18].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
b->pins[18].gpio.pullup_enable = 57;
b->pins[18].i2c.pinmap = 1;
b->pins[18].i2c.mux_total = 1;
b->pins[18].i2c.mux[0].pin = 60;
b->pins[18].i2c.mux[0].value = 0;
b->pins[18].aio.pinmap = 4;
b->pins[18].aio.mux_total = 3;
b->pins[18].aio.mux[0].pin = 60;
b->pins[18].aio.mux[0].value = 1;
b->pins[18].aio.mux[1].pin = 78;
b->pins[18].aio.mux[1].value = 0;
b->pins[18].aio.mux[2].pin = 57;
b->pins[18].aio.mux[2].value = 0;
b->pins[18].gpio.pinmap = 56;
b->pins[18].gpio.mux_total = 2;
b->pins[18].gpio.mux[0].pin = 60;
b->pins[18].gpio.mux[0].value = 1;
b->pins[18].gpio.mux[1].pin = 78;
b->pins[18].gpio.mux[1].value = 1;
strncpy(b->pins[19].name, "A5", 8);
b->pins[19].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,1};
b->pins[19].gpio.complex_cap = (mraa_pin_cap_complex_t) {1,0,0,1,1};
b->pins[19].gpio.pullup_enable = 59;
b->pins[19].i2c.pinmap = 1;
b->pins[19].i2c.mux_total = 1;
b->pins[19].i2c.mux[0].pin = 60;
b->pins[19].i2c.mux[0].value = 0;
b->pins[19].aio.pinmap = 5;
b->pins[19].aio.mux_total = 3;
b->pins[19].aio.mux[0].pin = 60;
b->pins[19].aio.mux[0].value = 1;
b->pins[19].aio.mux[1].pin = 79;
b->pins[19].aio.mux[1].value = 0;
b->pins[19].aio.mux[2].pin = 59;
b->pins[19].aio.mux[2].value = 1;
b->pins[19].gpio.pinmap = 58;
b->pins[19].gpio.mux_total = 2;
b->pins[19].gpio.mux[0].pin = 60;
b->pins[19].gpio.mux[0].value = 1;
b->pins[19].gpio.mux[1].pin = 79;
b->pins[19].gpio.mux[1].value = 1;
//BUS DEFINITIONS
b->i2c_bus_count = 1;
b->def_i2c_bus = 0;
b->i2c_bus[0].bus_id = 0;
b->i2c_bus[0].sda = 18;
b->i2c_bus[0].scl = 19;
b->spi_bus_count = 1;
b->def_spi_bus = 0;
b->spi_bus[0].bus_id = 1;
b->spi_bus[0].slave_s = 0;
b->spi_bus[0].cs = 10;
b->spi_bus[0].mosi = 11;
b->spi_bus[0].miso = 12;
b->spi_bus[0].sclk = 13;
b->uart_dev_count = 1;
b->def_uart_dev = 0;
b->uart_dev[0].rx = 0;
b->uart_dev[0].tx = 1;
return b;
error:
syslog(LOG_CRIT, "galileo2: Platform failed to initialise");
free(b);
return NULL;
}

165
src/x86/intel_minnow_max.c Normal file
View File

@@ -0,0 +1,165 @@
/*
* Author: Henry Bruce <henry.bruce@intel.com>
* Copyright (c) 2014 Intel Corporation.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <stdlib.h>
#include <string.h>
#include "common.h"
#include "intel_minnow_max.h"
#define PLATFORM_NAME "MinnowBoard MAX"
#define I2C_BUS_COUNT 10
#define I2C_BUS_DEFAULT 7
mraa_result_t
mraa_set_pininfo(mraa_board_t* board, int mraa_index, char *name, mraa_pincapabilities_t caps, int sysfs_pin)
{
if (mraa_index < board->phy_pin_count) {
mraa_pininfo_t* pin_info = &board->pins[mraa_index];
strncpy(pin_info->name, name, 7);
pin_info->capabilites = caps;
if (caps.gpio)
pin_info->gpio.pinmap = sysfs_pin;
if (caps.i2c) {
pin_info->i2c.pinmap = 1;
pin_info->i2c.mux_total = 0;
}
if (caps.pwm) {
int controller = 0;
if (strncmp(name, "PWM", 3) == 0 && strlen(name) > 3 && isdigit(name[3]))
controller = name[3] - '0';
pin_info->pwm.parent_id = controller;
pin_info->pwm.pinmap = 0;
pin_info->pwm.mux_total = 0;
}
return MRAA_SUCCESS;
}
return MRAA_ERROR_INVALID_RESOURCE;
}
mraa_result_t
mraa_get_pin_index(mraa_board_t* board, char *name, int* pin_index) {
int i;
for (i = 0; i < board->phy_pin_count; ++i) {
if (strcmp(name, board->pins[i].name) == 0) {
*pin_index = i;
return MRAA_SUCCESS;
}
}
return MRAA_ERROR_INVALID_RESOURCE;
}
mraa_board_t*
mraa_intel_minnow_max()
{
mraa_board_t* b = (mraa_board_t*) malloc(sizeof(mraa_board_t));
if (b == NULL) {
return NULL;
}
b->platform_name_length = strlen(PLATFORM_NAME) + 1;
b->platform_name = (char*) malloc(sizeof(char) * b->platform_name_length);
if (b->platform_name == NULL) {
goto error;
}
strncpy(b->platform_name, PLATFORM_NAME, b->platform_name_length);
b->phy_pin_count = MRAA_INTEL_MINNOW_MAX_PINCOUNT;
//b->gpio_count = 14;
b->aio_count = 0;
b->adc_raw = 0;
b->adc_supported = 0;
b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t)*MRAA_INTEL_MINNOW_MAX_PINCOUNT);
if (b->pins == NULL) {
goto error;
}
mraa_set_pininfo(b, 0, "INVALID", (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, -1);
mraa_set_pininfo(b, 1, "GND", (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, -1);
mraa_set_pininfo(b, 2, "GND", (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, -1);
mraa_set_pininfo(b, 3, "5v", (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, -1);
mraa_set_pininfo(b, 4, "3.3v", (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, -1);
mraa_set_pininfo(b, 5, "SPI_CS", (mraa_pincapabilities_t){1,0,0,0,1,0,0,0}, 220);
mraa_set_pininfo(b, 6, "UART1TX", (mraa_pincapabilities_t){1,0,0,0,0,0,0,1}, 225);
mraa_set_pininfo(b, 7, "SPIMISO", (mraa_pincapabilities_t){1,0,0,0,1,0,0,0}, 221);
mraa_set_pininfo(b, 8, "UART1RX", (mraa_pincapabilities_t){1,0,0,0,0,0,0,1}, 224);
mraa_set_pininfo(b, 9, "SPIMOSI", (mraa_pincapabilities_t){1,0,0,0,1,0,0,0}, 222);
mraa_set_pininfo(b, 10, "UART1CT", (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, 227);
mraa_set_pininfo(b, 11, "SPI_CLK", (mraa_pincapabilities_t){1,0,0,0,0,0,0,1}, 223);
mraa_set_pininfo(b, 12, "UART1RT", (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, 226);
mraa_set_pininfo(b, 13, "I2C_SCL", (mraa_pincapabilities_t){1,0,0,0,0,1,0,0}, 243);
mraa_set_pininfo(b, 14, "I2S_CLK", (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, 216);
mraa_set_pininfo(b, 15, "I2C_SDA", (mraa_pincapabilities_t){1,0,0,0,0,1,0,0}, 242);
mraa_set_pininfo(b, 16, "I2S_FRM", (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, 217);
mraa_set_pininfo(b, 17, "UART2TX", (mraa_pincapabilities_t){1,0,0,0,0,0,0,1}, 229);
mraa_set_pininfo(b, 18, "I2S_DO", (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, 219);
mraa_set_pininfo(b, 19, "UART2RX", (mraa_pincapabilities_t){1,0,0,0,0,0,0,1}, 228);
mraa_set_pininfo(b, 20, "I2S_DI", (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, 218);
mraa_set_pininfo(b, 21, "S5_0", (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, 82);
mraa_set_pininfo(b, 22, "PWM0", (mraa_pincapabilities_t){1,0,1,0,0,0,0,0}, 248); // Assume BIOS configured for PWM
mraa_set_pininfo(b, 23, "S5_1", (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, 83);
mraa_set_pininfo(b, 24, "PWM1", (mraa_pincapabilities_t){1,0,1,0,0,0,0,0}, 249); // Assume BIOS configured for PWM
mraa_set_pininfo(b, 25, "S5_4", (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, 84);
mraa_set_pininfo(b, 26, "IBL8254", (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, 208);
// Set number of i2c adaptors
// Got this from running 'i2cdetect -l'
b->i2c_bus_count = I2C_BUS_COUNT;
// Disable all i2c adaptors
int ici;
for (ici = 0; ici < b->i2c_bus_count; ici++) {
b->i2c_bus[ici].bus_id = -1;
}
// Configure i2c adaptor #7 and make it the default
int pin_index_sda, pin_index_scl;
if (mraa_get_pin_index(b, "I2C_SDA", &pin_index_sda) == MRAA_SUCCESS &&
mraa_get_pin_index(b, "I2C_SCL", &pin_index_scl) == MRAA_SUCCESS) {
b->def_i2c_bus = I2C_BUS_DEFAULT;
b->i2c_bus[b->def_i2c_bus].bus_id = b->def_i2c_bus;
b->i2c_bus[b->def_i2c_bus].sda = pin_index_sda;
b->i2c_bus[b->def_i2c_bus].scl = pin_index_scl;
}
// Configure PWM
b->pwm_default_period = 500;
b->pwm_max_period = 1000000000;
b->pwm_min_period = 1;
b->spi_bus_count = 1;
b->def_spi_bus = 0;
b->spi_bus[0].bus_id = 0;
b->spi_bus[0].slave_s = 0;
b->spi_bus[0].cs = 5;
b->spi_bus[0].mosi = 9;
b->spi_bus[0].miso = 7;
b->spi_bus[0].sclk = 11;
return b;
error:
syslog(LOG_CRIT, "minnowmax: Platform failed to initialise");
free(b);
return NULL;
}

86
src/x86/x86.c Normal file
View File

@@ -0,0 +1,86 @@
/*
* Author: Thomas Ingleby <thomas.c.ingleby@intel.com>
* Copyright (c) 2014 Intel Corporation.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <stdlib.h>
#include "mraa_internal.h"
#include "intel_galileo_rev_d.h"
#include "intel_galileo_rev_g.h"
#include "intel_edison_fab_c.h"
#include "intel_de3815.h"
#include "intel_minnow_max.h"
mraa_platform_t
mraa_x86_platform()
{
mraa_platform_t platform_type = MRAA_UNKNOWN_PLATFORM;
char *line = NULL;
// let getline allocate memory for *line
size_t len = 0;
FILE *fh = fopen("/sys/devices/virtual/dmi/id/board_name", "r");
if (fh != NULL) {
if (getline(&line, &len, fh) != -1) {
if (strncmp(line, "GalileoGen2", 11) == 0) {
platform_type = MRAA_INTEL_GALILEO_GEN2;
} else if (strncmp(line, "BODEGA BAY", 10) == 0) {
platform_type = MRAA_INTEL_EDISON_FAB_C;
} else if (strncmp(line, "SALT BAY", 8) == 0) {
platform_type = MRAA_INTEL_EDISON_FAB_C;
} else if (strncmp(line, "DE3815", 6) == 0) {
platform_type = MRAA_INTEL_DE3815;
} else if (strncmp(line, "NOTEBOOK", 8) == 0) {
platform_type = MRAA_INTEL_MINNOWBOARD_MAX;
} else if (strncasecmp(line, "MinnowBoard MAX", 15) == 0) {
platform_type = MRAA_INTEL_MINNOWBOARD_MAX;
} else {
platform_type = MRAA_INTEL_GALILEO_GEN1;
}
free(line);
}
fclose(fh);
}
switch(platform_type) {
case MRAA_INTEL_GALILEO_GEN2:
plat = mraa_intel_galileo_gen2();
break;
case MRAA_INTEL_GALILEO_GEN1:
plat = mraa_intel_galileo_rev_d();
break;
case MRAA_INTEL_EDISON_FAB_C:
plat = mraa_intel_edison_fab_c();
break;
case MRAA_INTEL_DE3815:
plat = mraa_intel_de3815();
break;
case MRAA_INTEL_MINNOWBOARD_MAX:
plat = mraa_intel_minnow_max();
break;
default:
plat = mraa_intel_galileo_rev_d();
syslog(LOG_ERR, "Platform not supported, initialising as MRAA_INTEL_GALILEO_GEN1");
}
return platform_type;
}