mraa_internal_types.h, aio.c, beaglebone.c:
Beaglebone AIO pins seem to be a little different than most boards, so this is my attempt to work with that without impacting other boards. I added a new flag in mraa_board_t to indicate whether or not the aio pins are sequential. One the beaglebone, they are not. To go along with this, I added a new device mraa_aio_dev_t, that will map each aio to a physical pin. In the main aio logic, if aio_non_seq is true for the board, the manual mapping is used, otherwise the old mathematical mapping is used. Signed-off-by: Nick Crast <nrcrast@gmail.com> Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
This commit is contained in:
committed by
Brendan Le Foll
parent
ff03b2de1d
commit
bb3584fcdb
@@ -107,8 +107,14 @@ mraa_aio_init(unsigned int aio)
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aio = mraa_get_sub_platform_index(aio);
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}
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// aio are always past the gpio_count in the pin array
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pin = aio + board->gpio_count;
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// Some boards, like the BBB, don't have sequential AIO pins
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// They will have their own specific mapping to map aio -> pin
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if((board->aio_non_seq) && (aio < board->aio_count)){
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pin = board->aio_dev[aio].pin;
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} else {
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// aio are always past the gpio_count in the pin array
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pin = aio + board->gpio_count;
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}
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if (pin < 0 || pin >= board->phy_pin_count) {
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syslog(LOG_ERR, "aio: pin %i beyond platform definition", pin);
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@@ -198,7 +198,6 @@ set_pin_mode(int pin, const char* mode)
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return MRAA_SUCCESS;
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}
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mraa_result_t
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mraa_beaglebone_uart_init_pre(int index)
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{
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@@ -1341,27 +1340,34 @@ mraa_beaglebone()
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// TODO AIN4
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strncpy(b->pins[BUILD_PIN(P9, 33)].name, "AIN4", MRAA_PIN_NAME_SIZE);
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b->pins[BUILD_PIN(P9, 33)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
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b->pins[BUILD_PIN(P9, 33)].aio.pinmap = 4;
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strncpy(b->pins[BUILD_PIN(P9, 34)].name, "GND_ADC", MRAA_PIN_NAME_SIZE);
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b->pins[BUILD_PIN(P9, 34)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
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// TODO AIN6
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strncpy(b->pins[BUILD_PIN(P9, 35)].name, "AIN6", MRAA_PIN_NAME_SIZE);
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b->pins[BUILD_PIN(P9, 35)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
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b->pins[BUILD_PIN(P9, 35)].aio.pinmap = 6;
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// TODO AIN5
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strncpy(b->pins[BUILD_PIN(P9, 36)].name, "AIN5", MRAA_PIN_NAME_SIZE);
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b->pins[BUILD_PIN(P9, 36)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
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b->pins[BUILD_PIN(P9, 36)].aio.pinmap = 5;
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// TODO AIN2
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strncpy(b->pins[BUILD_PIN(P9, 37)].name, "AIN2", MRAA_PIN_NAME_SIZE);
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b->pins[BUILD_PIN(P9, 37)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
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b->pins[BUILD_PIN(P9, 37)].aio.pinmap = 2;
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// TODO AIN3
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strncpy(b->pins[BUILD_PIN(P9, 38)].name, "AIN3", MRAA_PIN_NAME_SIZE);
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b->pins[BUILD_PIN(P9, 38)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
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b->pins[BUILD_PIN(P9, 38)].aio.pinmap = 3;
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// TODO AIN0
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strncpy(b->pins[BUILD_PIN(P9, 39)].name, "AIN0", MRAA_PIN_NAME_SIZE);
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b->pins[BUILD_PIN(P9, 39)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
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b->pins[BUILD_PIN(P9, 39)].aio.pinmap = 0;
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// TODO AIN1
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strncpy(b->pins[BUILD_PIN(P9, 40)].name, "AIN1", MRAA_PIN_NAME_SIZE);
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b->pins[BUILD_PIN(P9, 40)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
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b->pins[BUILD_PIN(P9, 40)].aio.pinmap = 1;
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strncpy(b->pins[BUILD_PIN(P9, 41)].name, "GPIO20", MRAA_PIN_NAME_SIZE);
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b->pins[BUILD_PIN(P9, 41)].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
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@@ -1445,13 +1451,18 @@ mraa_beaglebone()
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b->uart_dev[4].tx = BUILD_PIN(P8, 37);
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b->uart_dev[4].device_path = "/dev/ttyO5";
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b->gpio_count = 0;
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int i;
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for (i = 0; i < b->phy_pin_count; i++)
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if (b->pins[i].capabilities.gpio)
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b->gpio_count++;
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b->aio_non_seq = 1;
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b->aio_dev[0].pin = BUILD_PIN(P9, 39);
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b->aio_dev[1].pin = BUILD_PIN(P9, 40);
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b->aio_dev[2].pin = BUILD_PIN(P9, 37);
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b->aio_dev[3].pin = BUILD_PIN(P9, 38);
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b->aio_dev[4].pin = BUILD_PIN(P9, 33);
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b->aio_dev[5].pin = BUILD_PIN(P9, 36);
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b->aio_dev[6].pin = BUILD_PIN(P9, 35);
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b->gpio_count = 81;
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return b;
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error:
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syslog(LOG_CRIT, "Beaglebone: failed to initialize");
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free(b);
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