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mraa_internal_types.h, aio.c, beaglebone.c:

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Beaglebone AIO pins seem to be a little different than most boards, so
this is my attempt to work with that without impacting other boards. I
added a new flag in mraa_board_t to indicate whether or not the aio pins
are sequential. One the beaglebone, they are not. To go along with this,
I added a new device mraa_aio_dev_t, that will map each aio to a
physical pin.

In the main aio logic, if aio_non_seq is true for the board, the manual
mapping is used, otherwise the old mathematical mapping is used.

Signed-off-by: Nick Crast  <nrcrast@gmail.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
This commit is contained in:
Nick Crast
2017-05-31 11:58:14 -04:00
committed by Brendan Le Foll
parent ff03b2de1d
commit bb3584fcdb
3 changed files with 38 additions and 9 deletions
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10
src/aio/aio.c
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@@ -107,8 +107,14 @@ mraa_aio_init(unsigned int aio)
aio = mraa_get_sub_platform_index(aio);
}
// aio are always past the gpio_count in the pin array
pin = aio + board->gpio_count;
// Some boards, like the BBB, don't have sequential AIO pins
// They will have their own specific mapping to map aio -> pin
if((board->aio_non_seq) && (aio < board->aio_count)){
pin = board->aio_dev[aio].pin;
} else {
// aio are always past the gpio_count in the pin array
pin = aio + board->gpio_count;
}
if (pin < 0 || pin >= board->phy_pin_count) {
syslog(LOG_ERR, "aio: pin %i beyond platform definition", pin);