mraa_internal_types.h, aio.c, beaglebone.c:
Beaglebone AIO pins seem to be a little different than most boards, so this is my attempt to work with that without impacting other boards. I added a new flag in mraa_board_t to indicate whether or not the aio pins are sequential. One the beaglebone, they are not. To go along with this, I added a new device mraa_aio_dev_t, that will map each aio to a physical pin. In the main aio logic, if aio_non_seq is true for the board, the manual mapping is used, otherwise the old mathematical mapping is used. Signed-off-by: Nick Crast <nrcrast@gmail.com> Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
This commit is contained in:
committed by
Brendan Le Foll
parent
ff03b2de1d
commit
bb3584fcdb
@@ -43,6 +43,7 @@
|
|||||||
// Max count for various busses
|
// Max count for various busses
|
||||||
#define MAX_I2C_BUS_COUNT 12
|
#define MAX_I2C_BUS_COUNT 12
|
||||||
#define MAX_SPI_BUS_COUNT 12
|
#define MAX_SPI_BUS_COUNT 12
|
||||||
|
#define MAX_AIO_COUNT 7
|
||||||
#define MAX_UART_COUNT 6
|
#define MAX_UART_COUNT 6
|
||||||
#define MAX_PWM_COUNT 6
|
#define MAX_PWM_COUNT 6
|
||||||
|
|
||||||
@@ -386,16 +387,25 @@ typedef struct {
|
|||||||
/*@}*/
|
/*@}*/
|
||||||
} mraa_pwm_dev_t;
|
} mraa_pwm_dev_t;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* A structure representing an aio device.
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
/*@{*/
|
||||||
|
unsigned int pin; /**< Pin as exposed in the system */
|
||||||
|
/*@}*/
|
||||||
|
} mraa_aio_dev_t;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* A Structure representing a platform/board.
|
* A Structure representing a platform/board.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
typedef struct _board_t {
|
typedef struct _board_t {
|
||||||
/*@{*/
|
/*@{*/
|
||||||
int phy_pin_count; /**< The Total IO pins on board */
|
int phy_pin_count; /**< The Total IO pins on board */
|
||||||
int gpio_count; /**< GPIO Count */
|
int gpio_count; /**< GPIO Count */
|
||||||
int aio_count; /**< Analog side Count */
|
int aio_count; /**< Analog side Count */
|
||||||
int i2c_bus_count; /**< Usable i2c Count */
|
int i2c_bus_count; /**< Usable i2c Count */
|
||||||
|
unsigned int aio_non_seq; /**< Are AIO pins non sequential? Usually 0. */
|
||||||
mraa_i2c_bus_t i2c_bus[MAX_I2C_BUS_COUNT]; /**< Array of i2c */
|
mraa_i2c_bus_t i2c_bus[MAX_I2C_BUS_COUNT]; /**< Array of i2c */
|
||||||
unsigned int def_i2c_bus; /**< Position in array of default i2c bus */
|
unsigned int def_i2c_bus; /**< Position in array of default i2c bus */
|
||||||
int spi_bus_count; /**< Usable spi Count */
|
int spi_bus_count; /**< Usable spi Count */
|
||||||
@@ -404,9 +414,11 @@ typedef struct _board_t {
|
|||||||
unsigned int adc_raw; /**< ADC raw bit value */
|
unsigned int adc_raw; /**< ADC raw bit value */
|
||||||
unsigned int adc_supported; /**< ADC supported bit value */
|
unsigned int adc_supported; /**< ADC supported bit value */
|
||||||
unsigned int def_uart_dev; /**< Position in array of default uart */
|
unsigned int def_uart_dev; /**< Position in array of default uart */
|
||||||
|
unsigned int def_aio_dev; /**< Position in array of default aio */
|
||||||
unsigned int def_pwm_dev; /**< Position in array of default pwm */
|
unsigned int def_pwm_dev; /**< Position in array of default pwm */
|
||||||
int uart_dev_count; /**< Usable uart Count */
|
int uart_dev_count; /**< Usable uart Count */
|
||||||
mraa_uart_dev_t uart_dev[MAX_UART_COUNT]; /**< Array of UARTs */
|
mraa_uart_dev_t uart_dev[MAX_UART_COUNT]; /**< Array of UARTs */
|
||||||
|
mraa_aio_dev_t aio_dev[MAX_AIO_COUNT]; /**<Array of AIOs */
|
||||||
mraa_boolean_t no_bus_mux; /**< i2c/spi/adc/pwm/uart bus muxing setup not required */
|
mraa_boolean_t no_bus_mux; /**< i2c/spi/adc/pwm/uart bus muxing setup not required */
|
||||||
int pwm_dev_count; /**< Usable pwm Count */
|
int pwm_dev_count; /**< Usable pwm Count */
|
||||||
mraa_pwm_dev_t pwm_dev[MAX_PWM_COUNT]; /**< Array of PWMs */
|
mraa_pwm_dev_t pwm_dev[MAX_PWM_COUNT]; /**< Array of PWMs */
|
||||||
|
|||||||
@@ -107,8 +107,14 @@ mraa_aio_init(unsigned int aio)
|
|||||||
aio = mraa_get_sub_platform_index(aio);
|
aio = mraa_get_sub_platform_index(aio);
|
||||||
}
|
}
|
||||||
|
|
||||||
// aio are always past the gpio_count in the pin array
|
// Some boards, like the BBB, don't have sequential AIO pins
|
||||||
pin = aio + board->gpio_count;
|
// They will have their own specific mapping to map aio -> pin
|
||||||
|
if((board->aio_non_seq) && (aio < board->aio_count)){
|
||||||
|
pin = board->aio_dev[aio].pin;
|
||||||
|
} else {
|
||||||
|
// aio are always past the gpio_count in the pin array
|
||||||
|
pin = aio + board->gpio_count;
|
||||||
|
}
|
||||||
|
|
||||||
if (pin < 0 || pin >= board->phy_pin_count) {
|
if (pin < 0 || pin >= board->phy_pin_count) {
|
||||||
syslog(LOG_ERR, "aio: pin %i beyond platform definition", pin);
|
syslog(LOG_ERR, "aio: pin %i beyond platform definition", pin);
|
||||||
|
|||||||
@@ -198,7 +198,6 @@ set_pin_mode(int pin, const char* mode)
|
|||||||
return MRAA_SUCCESS;
|
return MRAA_SUCCESS;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
mraa_result_t
|
mraa_result_t
|
||||||
mraa_beaglebone_uart_init_pre(int index)
|
mraa_beaglebone_uart_init_pre(int index)
|
||||||
{
|
{
|
||||||
@@ -1341,27 +1340,34 @@ mraa_beaglebone()
|
|||||||
// TODO AIN4
|
// TODO AIN4
|
||||||
strncpy(b->pins[BUILD_PIN(P9, 33)].name, "AIN4", MRAA_PIN_NAME_SIZE);
|
strncpy(b->pins[BUILD_PIN(P9, 33)].name, "AIN4", MRAA_PIN_NAME_SIZE);
|
||||||
b->pins[BUILD_PIN(P9, 33)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
|
b->pins[BUILD_PIN(P9, 33)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
|
||||||
|
b->pins[BUILD_PIN(P9, 33)].aio.pinmap = 4;
|
||||||
|
|
||||||
strncpy(b->pins[BUILD_PIN(P9, 34)].name, "GND_ADC", MRAA_PIN_NAME_SIZE);
|
strncpy(b->pins[BUILD_PIN(P9, 34)].name, "GND_ADC", MRAA_PIN_NAME_SIZE);
|
||||||
b->pins[BUILD_PIN(P9, 34)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
|
b->pins[BUILD_PIN(P9, 34)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
|
||||||
// TODO AIN6
|
// TODO AIN6
|
||||||
strncpy(b->pins[BUILD_PIN(P9, 35)].name, "AIN6", MRAA_PIN_NAME_SIZE);
|
strncpy(b->pins[BUILD_PIN(P9, 35)].name, "AIN6", MRAA_PIN_NAME_SIZE);
|
||||||
b->pins[BUILD_PIN(P9, 35)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
|
b->pins[BUILD_PIN(P9, 35)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
|
||||||
|
b->pins[BUILD_PIN(P9, 35)].aio.pinmap = 6;
|
||||||
// TODO AIN5
|
// TODO AIN5
|
||||||
strncpy(b->pins[BUILD_PIN(P9, 36)].name, "AIN5", MRAA_PIN_NAME_SIZE);
|
strncpy(b->pins[BUILD_PIN(P9, 36)].name, "AIN5", MRAA_PIN_NAME_SIZE);
|
||||||
b->pins[BUILD_PIN(P9, 36)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
|
b->pins[BUILD_PIN(P9, 36)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
|
||||||
|
b->pins[BUILD_PIN(P9, 36)].aio.pinmap = 5;
|
||||||
// TODO AIN2
|
// TODO AIN2
|
||||||
strncpy(b->pins[BUILD_PIN(P9, 37)].name, "AIN2", MRAA_PIN_NAME_SIZE);
|
strncpy(b->pins[BUILD_PIN(P9, 37)].name, "AIN2", MRAA_PIN_NAME_SIZE);
|
||||||
b->pins[BUILD_PIN(P9, 37)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
|
b->pins[BUILD_PIN(P9, 37)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
|
||||||
|
b->pins[BUILD_PIN(P9, 37)].aio.pinmap = 2;
|
||||||
// TODO AIN3
|
// TODO AIN3
|
||||||
strncpy(b->pins[BUILD_PIN(P9, 38)].name, "AIN3", MRAA_PIN_NAME_SIZE);
|
strncpy(b->pins[BUILD_PIN(P9, 38)].name, "AIN3", MRAA_PIN_NAME_SIZE);
|
||||||
b->pins[BUILD_PIN(P9, 38)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
|
b->pins[BUILD_PIN(P9, 38)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
|
||||||
|
b->pins[BUILD_PIN(P9, 38)].aio.pinmap = 3;
|
||||||
// TODO AIN0
|
// TODO AIN0
|
||||||
strncpy(b->pins[BUILD_PIN(P9, 39)].name, "AIN0", MRAA_PIN_NAME_SIZE);
|
strncpy(b->pins[BUILD_PIN(P9, 39)].name, "AIN0", MRAA_PIN_NAME_SIZE);
|
||||||
b->pins[BUILD_PIN(P9, 39)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
|
b->pins[BUILD_PIN(P9, 39)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
|
||||||
|
b->pins[BUILD_PIN(P9, 39)].aio.pinmap = 0;
|
||||||
// TODO AIN1
|
// TODO AIN1
|
||||||
strncpy(b->pins[BUILD_PIN(P9, 40)].name, "AIN1", MRAA_PIN_NAME_SIZE);
|
strncpy(b->pins[BUILD_PIN(P9, 40)].name, "AIN1", MRAA_PIN_NAME_SIZE);
|
||||||
b->pins[BUILD_PIN(P9, 40)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
|
b->pins[BUILD_PIN(P9, 40)].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 1, 0 };
|
||||||
|
b->pins[BUILD_PIN(P9, 40)].aio.pinmap = 1;
|
||||||
|
|
||||||
strncpy(b->pins[BUILD_PIN(P9, 41)].name, "GPIO20", MRAA_PIN_NAME_SIZE);
|
strncpy(b->pins[BUILD_PIN(P9, 41)].name, "GPIO20", MRAA_PIN_NAME_SIZE);
|
||||||
b->pins[BUILD_PIN(P9, 41)].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
|
b->pins[BUILD_PIN(P9, 41)].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
|
||||||
@@ -1445,13 +1451,18 @@ mraa_beaglebone()
|
|||||||
b->uart_dev[4].tx = BUILD_PIN(P8, 37);
|
b->uart_dev[4].tx = BUILD_PIN(P8, 37);
|
||||||
b->uart_dev[4].device_path = "/dev/ttyO5";
|
b->uart_dev[4].device_path = "/dev/ttyO5";
|
||||||
|
|
||||||
b->gpio_count = 0;
|
b->aio_non_seq = 1;
|
||||||
int i;
|
b->aio_dev[0].pin = BUILD_PIN(P9, 39);
|
||||||
for (i = 0; i < b->phy_pin_count; i++)
|
b->aio_dev[1].pin = BUILD_PIN(P9, 40);
|
||||||
if (b->pins[i].capabilities.gpio)
|
b->aio_dev[2].pin = BUILD_PIN(P9, 37);
|
||||||
b->gpio_count++;
|
b->aio_dev[3].pin = BUILD_PIN(P9, 38);
|
||||||
|
b->aio_dev[4].pin = BUILD_PIN(P9, 33);
|
||||||
|
b->aio_dev[5].pin = BUILD_PIN(P9, 36);
|
||||||
|
b->aio_dev[6].pin = BUILD_PIN(P9, 35);
|
||||||
|
b->gpio_count = 81;
|
||||||
|
|
||||||
return b;
|
return b;
|
||||||
|
|
||||||
error:
|
error:
|
||||||
syslog(LOG_CRIT, "Beaglebone: failed to initialize");
|
syslog(LOG_CRIT, "Beaglebone: failed to initialize");
|
||||||
free(b);
|
free(b);
|
||||||
|
|||||||
Reference in New Issue
Block a user