docs: update product names & brand names
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
This commit is contained in:
@@ -1,8 +1,8 @@
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Intel Edison {#edison}
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Intel Edison {#edison}
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=============
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=============
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Edison is a dual core Silvermont Atom clocked at 500MHz. The Edison
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Intel(R) Edison is a dual core Silvermont Atom(TM) clocked at 500MHz. The
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also features 4GB of storage, 1GB ram and onboard wifi and bluetooth.
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Edison also features 4GB of storage, 1GB ram and onboard wifi and bluetooth.
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Currently Supported boards:
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Currently Supported boards:
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- Intel Arduino board
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- Intel Arduino board
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@@ -25,8 +25,8 @@ in libmraa:
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- AIO pins are treated as 0-5 in mraa_aio_init() but as 14-19 for everything
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- AIO pins are treated as 0-5 in mraa_aio_init() but as 14-19 for everything
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else. Therefore use mraa_gpio_init(14) to use A0 as a Gpio
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else. Therefore use mraa_gpio_init(14) to use A0 as a Gpio
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Intel breakout board
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Intel(R) breakout board
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--------------------
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-----------------------
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- Both I2C buses are avaible 1 & 6
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- Both I2C buses are avaible 1 & 6
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- IO on the miniboard is 1.8V
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- IO on the miniboard is 1.8V
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@@ -1,7 +1,7 @@
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Galileo Gen 1 - Rev D {#galileorevd}
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Galileo Gen 1 - Rev D {#galileorevd}
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=====================
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=====================
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Galileo is a microcontroller board based on the Intel® Quark SoC X1000
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Galileo is a microcontroller board based on the Intel(R) Quark(TM) SoC X1000
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Application Processor, a 32-bit Intel Pentium-class system on a chip.
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Application Processor, a 32-bit Intel Pentium-class system on a chip.
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The rev D board has the following limitations in libmraa:
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The rev D board has the following limitations in libmraa:
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@@ -1,7 +1,7 @@
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Galileo Gen 2 - Rev H {#galileorevh}
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Galileo Gen 2 - Rev H {#galileorevh}
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=====================
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=====================
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Galileo is a microcontroller board based on the Intel® Quark SoC X1000
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Galileo is a microcontroller board based on the Intel(R) Quark(TM) SoC X1000
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Application Processor, a 32-bit Intel Pentium-class system on a chip.
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Application Processor, a 32-bit Intel Pentium-class system on a chip.
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The Gen 2 board has the following limitations in libmraa:
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The Gen 2 board has the following limitations in libmraa:
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@@ -1,7 +1,7 @@
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Intel NUC DE3815tykhe {#de3815}
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Intel(R) NUC DE3815tykhe {#de3815}
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=============
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=============
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The DE3815 NUC Kit is a single core Atom clocked at 1.46GHz.
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The DE3815 NUC Kit is a single core Atom(TM) clocked at 1.46GHz.
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http://www.intel.com/content/www/us/en/nuc/nuc-kit-de3815tykhe.html
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http://www.intel.com/content/www/us/en/nuc/nuc-kit-de3815tykhe.html
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Interface notes
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Interface notes
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@@ -1,8 +1,10 @@
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Intel Minnowboard Max {#minnowmax}
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Intel(R) Minnowboard Max {#minnowmax}
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=====================
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========================
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MinnowBoard MAX is an open hardware embedded board designed with the Intel® Atom™ E38xx series SOC (known as Bay Trail).
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MinnowBoard MAX is an open hardware embedded board designed with the Intel(R)
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Atom(TM) E38xx series SOC (Fromerly Bay Trail).
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For product overview and faq see http://www.minnowboard.org/faq-minnowboard-max/
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For product overview and faq see
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http://www.minnowboard.org/faq-minnowboard-max/
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For technical details see http://www.elinux.org/Minnowboard:MinnowMax
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For technical details see http://www.elinux.org/Minnowboard:MinnowMax
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@@ -12,12 +14,13 @@ mraa has only been tested with 64 bit firmware version 0.73 or later.
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Interface notes
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Interface notes
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---------------
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---------------
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The low speed I/O connector supported as per table below.
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The low speed I/O connector supported as per table below. This assumes default
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This assumes default BIOS settings, as they are not dynamcially detected
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BIOS settings, as they are not dynamcially detected If any changes are mode
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If any changes are mode (Device Manager -> System Setup -> South Cluster -> LPSS & CSS)
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(Device Manager -> System Setup -> South Cluster -> LPSS & CSS) them mraa calls
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them mraa calls will not behave as expected.
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will not behave as expected.
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Documentation shows i2c on bus #5, ACPI shows it on bus #6, but driver uses bus #7.
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Documentation shows i2c on bus #5, ACPI shows it on bus #6, but driver uses bus
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#7.
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**SPI operation is not currently supported**
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**SPI operation is not currently supported**
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