From d055b45b7e0744de60855f35007999dded684945 Mon Sep 17 00:00:00 2001 From: nascs Date: Wed, 11 Oct 2023 10:32:50 +0000 Subject: [PATCH] platform: add Radxa CM5 IO platform support Signed-off-by: Nascs --- README.md | 1 + api/mraa/types.h | 33 +++++++- api/mraa/types.hpp | 32 +++++++ docs/index.java.md | 1 + docs/index.md | 1 + docs/radxa_cm5_io.md | 47 +++++++++++ include/arm/radxa_cm5_io.h | 30 +++++++ src/CMakeLists.txt | 1 + src/arm/arm.c | 6 ++ src/arm/radxa_cm5_io.c | 166 +++++++++++++++++++++++++++++++++++++ 10 files changed, 317 insertions(+), 1 deletion(-) create mode 100644 docs/radxa_cm5_io.md create mode 100644 include/arm/radxa_cm5_io.h create mode 100644 src/arm/radxa_cm5_io.c diff --git a/README.md b/README.md index b333d25..7c5fc3d 100644 --- a/README.md +++ b/README.md @@ -50,6 +50,7 @@ ARM * [Radxa ROCK 3C](../master/docs/radxa_rock_3c.md) * [Radxa ROCK 5A](../master/docs/radxa_rock_5a.md) * [Radxa ROCK 5B](../master/docs/radxa_rock_5b.md) +* [Radxa CM5 IO](../master/docs/radxa_cm5_io.md) * [Rock Pi 4](../master/docs/rockpi4.md) * [Orange Pi Prime](../master/docs/orange_pi_prime.md) diff --git a/api/mraa/types.h b/api/mraa/types.h index 818a0dd..312ee0e 100644 --- a/api/mraa/types.h +++ b/api/mraa/types.h @@ -76,6 +76,7 @@ typedef enum { MRAA_ORANGE_PI_PRIME = 31, /**< Orange Pi Prime board */ MRAA_RADXA_ROCK_3B = 32, /**< Radxa ROCK 3 Model B */ MRAA_RADXA_CM3 = 33, /**< Radxa CM3 */ + MRAA_RADXA_CM5_IO = 34, /**< Radxa CM5 IO */ // USB platform extenders start at 256 MRAA_FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */ @@ -251,6 +252,37 @@ typedef enum { MRAA_RADXA_ROCK_5B_PIN40 = 40 } mraa_radxa_rock_5b_wiring_t; +/** + * Radxa CM5 IO GPIO numbering enum + */ +typedef enum { + RADXA_CM5_IO_PIN3 = 3, + RADXA_CM5_IO_PIN5 = 5, + RADXA_CM5_IO_PIN7 = 7, + RADXA_CM5_IO_PIN8 = 8, + RADXA_CM5_IO_PIN10 = 10, + RADXA_CM5_IO_PIN11 = 11, + RADXA_CM5_IO_PIN12 = 12, + RADXA_CM5_IO_PIN13 = 13, + RADXA_CM5_IO_PIN15 = 15, + RADXA_CM5_IO_PIN16 = 16, + RADXA_CM5_IO_PIN18 = 18, + RADXA_CM5_IO_PIN19 = 19, + RADXA_CM5_IO_PIN21 = 21, + RADXA_CM5_IO_PIN22 = 22, + RADXA_CM5_IO_PIN23 = 23, + RADXA_CM5_IO_PIN24 = 24, + RADXA_CM5_IO_PIN26 = 26, + RADXA_CM5_IO_PIN29 = 29, + RADXA_CM5_IO_PIN31 = 31, + RADXA_CM5_IO_PIN32 = 32, + RADXA_CM5_IO_PIN33 = 33, + RADXA_CM5_IO_PIN35 = 35, + RADXA_CM5_IO_PIN36 = 36, + RADXA_CM5_IO_PIN38 = 38, + RADXA_CM5_IO_PIN40 = 40 +} mraa_radxa_cm5_io_wiring_t; + /** * Radxa ROCK 3 Model B GPIO numbering enum */ @@ -283,7 +315,6 @@ typedef enum { RADXA_ROCK_3B_PIN40 = 40 } mraa_radxa_rock_3b_wiring_t; - /** * Radxa ROCK 3 Model C GPIO numbering enum */ diff --git a/api/mraa/types.hpp b/api/mraa/types.hpp index 86a7075..41d281b 100644 --- a/api/mraa/types.hpp +++ b/api/mraa/types.hpp @@ -70,6 +70,7 @@ typedef enum { ORANGE_PI_PRIME = 31, /**< Orange Pi Prime board */ RADXA_ROCK_3B = 32, /**< Radxa ROCK 3 Model B */ RADXA_CM3 = 33, /**< Radxa CM3 */ + RADXA_CM5_IO = 34, /**< Radxa CM5 IO */ FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */ @@ -242,6 +243,37 @@ typedef enum { RADXA_ROCK_5B_PIN40 = 40 } RadxaRock5BWiring; +/** + * Radxa CM5 IO GPIO numbering enum + */ +typedef enum { + RADXA_CM5_IO_PIN3 = 3, + RADXA_CM5_IO_PIN5 = 5, + RADXA_CM5_IO_PIN7 = 7, + RADXA_CM5_IO_PIN8 = 8, + RADXA_CM5_IO_PIN10 = 10, + RADXA_CM5_IO_PIN11 = 11, + RADXA_CM5_IO_PIN12 = 12, + RADXA_CM5_IO_PIN13 = 13, + RADXA_CM5_IO_PIN15 = 15, + RADXA_CM5_IO_PIN16 = 16, + RADXA_CM5_IO_PIN18 = 18, + RADXA_CM5_IO_PIN19 = 19, + RADXA_CM5_IO_PIN21 = 21, + RADXA_CM5_IO_PIN22 = 22, + RADXA_CM5_IO_PIN23 = 23, + RADXA_CM5_IO_PIN24 = 24, + RADXA_CM5_IO_PIN26 = 26, + RADXA_CM5_IO_PIN29 = 29, + RADXA_CM5_IO_PIN31 = 31, + RADXA_CM5_IO_PIN32 = 32, + RADXA_CM5_IO_PIN33 = 33, + RADXA_CM5_IO_PIN35 = 35, + RADXA_CM5_IO_PIN36 = 36, + RADXA_CM5_IO_PIN38 = 38, + RADXA_CM5_IO_PIN40 = 40 +} RadxaCM5IOWiring; + /** * Radxa ROCK 3 Model B GPIO numbering enum */ diff --git a/docs/index.java.md b/docs/index.java.md index e3d8cbe..cee6243 100644 --- a/docs/index.java.md +++ b/docs/index.java.md @@ -55,6 +55,7 @@ Specific platform information for supported platforms is documented here: - @ref up-xtreme - @ref _orange_pi_prime - @ref radxa_cm3 +- @ref radxa_cm5_io - @ref radxa_rock_3b - @ref radxa_rock_3c - @ref radxa_rock_5a diff --git a/docs/index.md b/docs/index.md index 01fa6d0..7e9ae7c 100644 --- a/docs/index.md +++ b/docs/index.md @@ -63,6 +63,7 @@ Specific platform information for supported platforms is documented here: - @ref upXtreme - @ref _orange_pi_prime - @ref radxa_cm3 +- @ref radxa_cm5_io - @ref radxa_rock_3b - @ref radxa_rock_3c - @ref radxa_rock_5a diff --git a/docs/radxa_cm5_io.md b/docs/radxa_cm5_io.md new file mode 100644 index 0000000..5d248fd --- /dev/null +++ b/docs/radxa_cm5_io.md @@ -0,0 +1,47 @@ +Radxa CM5 IO {#_Radxa} +============ + +The Radxa CM5 is a System on Module (SoM) based on the Rockchip RK3588s System on Chip (SoC). CM5 is compatible with Radxa CM5 IO Board. It can run android or some Linux distributions. Radxa CM5 IO features an eight core ARM processor, 64bit dual channel 3200Mb/s LPDDR4, up to 8Kp60 HDMI, MIPI DSI, MIPI CSI, 3.5mm jack with mic, 802.11 ac WIFI, Bluetooth 5.0, USB Port, GbE LAN, 40-pin color expansion header, RTC. Also, Radxa CM5 IO supports USB PD and QC powering. + +Interface notes +--------------- + +- UART2 is enabled as the default console. +- All UART ports support baud up to 1500000. + +Pin Mapping +----------- + +Radxa CM5 IO has a 40-pin expansion header. Each pin is distinguished by color. + +|Function4 |Function3 |Function2 |Function1 | | PIN | PIN | Function1| Function2| Function3| +|------------|------------|------------|-----------|:------|------:|---------|------------|-----------|------------| +| | | |+3.3V | 1 | 2 | +5.0V| | | | +| | |I2C7_SDA_M2 |GPIO3_D3 | 3 | 4 | +5.0V| | | | +| | |I2C7_SCL_M2 |GPIO3_D2 | 5 | 6 | GND| | | | +| | |I2C5_SDA_M2 |GPIO4_A7 | 7 | 8 | GPIO0_B5| UART2_TX_M0|I2C1_SCL_M0| | +| | | |GND | 9 | 10 | GPIO0_B6| UART2_RX_M0|I2C1_SDA_M0| | +| |UART3_RX_M2 |I2C5_SCL_M2 |GPIO4_A6 | 11 | 12 | GPIO0_C2| | | | +| |UART3_TX_M2 |I2C3_SDA_M2 |GPIO4_A5 | 13 | 14 | GND| | | | +| | |I2C3_SCL_M2 |GPIO4_A4 | 15 | 16 | GPIO1_C4| PWM11_IR_M2| | | +| | | |+3.3V | 17 | 18 | GPIO1_D5| | | | +| | |SPI0_MOSI_M1|GPIO4_A1 | 19 | 20 | GND| | | | +| | |SPI0_MISO_M1|GPIO4_A0 | 21 | 22 | GPIO1_B1| | | | +| | |SPI0_CLK_M1 |GPIO4_A2 | 23 | 24 | GPIO4_B2| SPI0_CS0_M1| PWM14_M1| | +| | | |GND | 25 | 26 | GPIO3_B7| | | | +| | | |+3.3V | 27 | 28 | +3.3V| | | | +| | |PWM7_IR_M0 |GPIO0_D0 | 29 | 30 | GND| | | | +| | |PWM6_M0 |GPIO0_C7 | 31 | 32 | GPIO1_B7| PWM13_M2| | | +| | | |GPIO1_C1 | 33 | 34 | GND| | | | +| | | |GPIO3_C0 | 35 | 36 | GPIO1_C6| PWM15_IR_M2| | | +| | | |SARADC_VIN4| 37 | 38 | GPIO1_D2| PWM0_M1| | | +| | | |GND | 39 | 40 | GPIO0_D3| | | | + +Resources +--------- + +You can find additional product support in the following channels: + +- [Product Info](https://docs.radxa.com/compute-module/cm5) +- [Forums](https://forum.radxa.com/c/rock5) +- [Github](https://github.com/radxa) diff --git a/include/arm/radxa_cm5_io.h b/include/arm/radxa_cm5_io.h new file mode 100644 index 0000000..5eee8ed --- /dev/null +++ b/include/arm/radxa_cm5_io.h @@ -0,0 +1,30 @@ +/* + * Author: Nascs + * Copyright (c) Radxa Limited. + * + * SPDX-License-Identifier: MIT + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "mraa_internal.h" + +#define MRAA_RADXA_CM5_IO_GPIO_COUNT 25 +#define MRAA_RADXA_CM5_IO_I2C_COUNT 4 +#define MRAA_RADXA_CM5_IO_SPI_COUNT 1 +#define MRAA_RADXA_CM5_IO_UART_COUNT 2 +#define MRAA_RADXA_CM5_IO_PWM_COUNT 7 +#define MRAA_RADXA_CM5_IO_AIO_COUNT 1 +#define MRAA_RADXA_CM5_IO_PIN_COUNT 40 +#define PLATFORM_NAME_RADXA_CM5_IO "Radxa CM5 IO" + +mraa_board_t * + mraa_radxa_cm5_io(); + +#ifdef __cplusplus +} +#endif diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 4480bfd..273c4be 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -112,6 +112,7 @@ set (mraa_LIB_ARM_SRCS_NOAUTO ${PROJECT_SOURCE_DIR}/src/arm/radxa_cm3.c ${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_5a.c ${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_5b.c + ${PROJECT_SOURCE_DIR}/src/arm/radxa_cm5_io.c ${PROJECT_SOURCE_DIR}/src/arm/rockpi4.c ${PROJECT_SOURCE_DIR}/src/arm/adlink_ipi.c ${PROJECT_SOURCE_DIR}/src/arm/siemens/iot2050.c diff --git a/src/arm/arm.c b/src/arm/arm.c index c7f3563..ccc5839 100644 --- a/src/arm/arm.c +++ b/src/arm/arm.c @@ -15,6 +15,7 @@ #include "arm/radxa_rock_3c.h" #include "arm/radxa_rock_5a.h" #include "arm/radxa_rock_5b.h" +#include "arm/radxa_cm5_io.h" #include "arm/rockpi4.h" #include "arm/de_nano_soc.h" #include "arm/banana.h" @@ -109,6 +110,8 @@ mraa_arm_platform() platform_type = MRAA_RADXA_ROCK_5A; else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_ROCK_5B)) platform_type = MRAA_RADXA_ROCK_5B; + else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_CM5_IO)) + platform_type = MRAA_RADXA_CM5_IO; else if (mraa_file_contains("/proc/device-tree/model", "ROCK Pi 4") || mraa_file_contains("/proc/device-tree/model", "ROCK PI 4") || mraa_file_contains("/proc/device-tree/model", "ROCK 4") @@ -155,6 +158,9 @@ mraa_arm_platform() case MRAA_RADXA_ROCK_5B: plat = mraa_radxa_rock_5b(); break; + case MRAA_RADXA_CM5_IO: + plat = mraa_radxa_cm5_io(); + break; case MRAA_ROCKPI4: plat = mraa_rockpi4(); break; diff --git a/src/arm/radxa_cm5_io.c b/src/arm/radxa_cm5_io.c new file mode 100644 index 0000000..178d919 --- /dev/null +++ b/src/arm/radxa_cm5_io.c @@ -0,0 +1,166 @@ +/* + * Author: Nascs + * Copyright (c) Radxa Limited. + * + * SPDX-License-Identifier: MIT + */ + +#include +#include +#include +#include +#include + +#include "arm/radxa_cm5_io.h" +#include "common.h" + +#define DT_BASE "/proc/device-tree" + +const char* radxa_cm5_io_serialdev[MRAA_RADXA_CM5_IO_UART_COUNT] = { "/dev/ttyS2", "/dev/ttyS3"}; + +void +mraa_radxa_cm5_io_pininfo(mraa_board_t* board, int index, int gpio_chip, int gpio_line, mraa_pincapabilities_t pincapabilities_t, char* pin_name) +{ + if (index > board->phy_pin_count) + return; + + mraa_pininfo_t* pininfo = &board->pins[index]; + strncpy(pininfo->name, pin_name, MRAA_PIN_NAME_SIZE); + + if(pincapabilities_t.gpio == 1) { + pininfo->gpio.gpio_chip = gpio_chip; + pininfo->gpio.gpio_line = gpio_line; + } + + pininfo->capabilities = pincapabilities_t; + + pininfo->gpio.mux_total = 0; +} + +mraa_board_t* +mraa_radxa_cm5_io() +{ + mraa_board_t* b = (mraa_board_t*) calloc(1, sizeof(mraa_board_t)); + if (b == NULL) { + return NULL; + } + + b->adv_func = (mraa_adv_func_t*) calloc(1, sizeof(mraa_adv_func_t)); + if (b->adv_func == NULL) { + free(b); + return NULL; + } + + // pin mux for buses are setup by default by kernel so tell mraa to ignore them + b->no_bus_mux = 1; + b->phy_pin_count = MRAA_RADXA_CM5_IO_PIN_COUNT + 1; + + // UART + b->uart_dev_count = MRAA_RADXA_CM5_IO_UART_COUNT; + b->platform_name = PLATFORM_NAME_RADXA_CM5_IO; + b->def_uart_dev = 0; + b->uart_dev[0].index = 2; + b->uart_dev[1].index = 3; + b->uart_dev[0].device_path = (char*) radxa_cm5_io_serialdev[0]; + b->uart_dev[1].device_path = (char*) radxa_cm5_io_serialdev[1]; + + // I2C + b->i2c_bus_count = MRAA_RADXA_CM5_IO_I2C_COUNT; + b->def_i2c_bus = 0; + b->i2c_bus[0].bus_id = 1; + b->i2c_bus[1].bus_id = 3; + b->i2c_bus[2].bus_id = 5; + b->i2c_bus[3].bus_id = 7; + + // SPI + b->spi_bus_count = MRAA_RADXA_CM5_IO_SPI_COUNT; + b->def_spi_bus = 0; + b->spi_bus[0].bus_id = 0; + + // PWM + b->pwm_dev_count = MRAA_RADXA_CM5_IO_PWM_COUNT; + b->pwm_default_period = 500; + b->pwm_max_period = 2147483; + b->pwm_min_period = 1; + + b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t) * b->phy_pin_count); + if (b->pins == NULL) { + free(b->adv_func); + free(b); + return NULL; + } + + b->pins[38].pwm.parent_id = 0; // PWM0-M1 + b->pins[38].pwm.mux_total = 0; + b->pins[38].pwm.pinmap = 0; + b->pins[31].pwm.parent_id = 6; // PWM6-M0 + b->pins[31].pwm.mux_total = 0; + b->pins[31].pwm.pinmap = 0; + b->pins[29].pwm.parent_id = 7; // PWM7-M0 + b->pins[29].pwm.mux_total = 0; + b->pins[29].pwm.pinmap = 0; + b->pins[16].pwm.parent_id = 11; // PWM11-M0 + b->pins[16].pwm.mux_total = 0; + b->pins[16].pwm.pinmap = 0; + b->pins[32].pwm.parent_id = 13; // PWM13-M2 + b->pins[32].pwm.mux_total = 0; + b->pins[32].pwm.pinmap = 0; + b->pins[24].pwm.parent_id = 11; // PWM14-M1 + b->pins[24].pwm.mux_total = 0; + b->pins[24].pwm.pinmap = 0; + b->pins[36].pwm.parent_id = 15; // PWM15-M2 + b->pins[36].pwm.mux_total = 0; + b->pins[36].pwm.pinmap = 0; + + // AIO + b->aio_count = MRAA_RADXA_CM5_IO_AIO_COUNT; + b->adc_raw = 10; + b->adc_supported = 10; + b->aio_dev[0].pin = 37; + b->aio_non_seq = 1; + b->chardev_capable = 1; + + mraa_radxa_cm5_io_pininfo(b, 0, -1, -1, (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, "INVALID"); + mraa_radxa_cm5_io_pininfo(b, 1, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3"); + mraa_radxa_cm5_io_pininfo(b, 2, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "5V"); + mraa_radxa_cm5_io_pininfo(b, 3, 3, 27, (mraa_pincapabilities_t){1,1,0,0,1,1,0,0}, "GPIO3_D3"); + mraa_radxa_cm5_io_pininfo(b, 4, -1, -1, (mraa_pincapabilities_t){1,0,0,0, 0,0,0,0}, "5V"); + mraa_radxa_cm5_io_pininfo(b, 5, 3, 26, (mraa_pincapabilities_t){1,1,0,0,1,1,0,0}, "GPIO3_D2"); + mraa_radxa_cm5_io_pininfo(b, 6, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_cm5_io_pininfo(b, 7, 4, 7, (mraa_pincapabilities_t){1,1,0,0,0,1,0,0}, "GPIO4_A7"); + mraa_radxa_cm5_io_pininfo(b, 8, 4, 13, (mraa_pincapabilities_t){1,0,0,0,0,1,0,1}, "GPIO0_B5"); // IO resources is occupied by uart, function GPIO can't be used. + mraa_radxa_cm5_io_pininfo(b, 9, -1, -1, (mraa_pincapabilities_t){1,0,0,0, 0,0,0,0}, "GND"); + mraa_radxa_cm5_io_pininfo(b, 10, 0, 14, (mraa_pincapabilities_t){1,0,0,0,0,1,0,1}, "GPIO0_B6"); // IO resources is occupied by uart, function GPIO can't be used. + mraa_radxa_cm5_io_pininfo(b, 11, 4, 6, (mraa_pincapabilities_t){1,1,0,0,0,1,0,1}, "GPIO4_A6"); + mraa_radxa_cm5_io_pininfo(b, 12, 0, 18, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO0_C2"); + mraa_radxa_cm5_io_pininfo(b, 13, 4, 5, (mraa_pincapabilities_t){1,1,0,0,0,1,0,1}, "GPIO4_A5"); + mraa_radxa_cm5_io_pininfo(b, 14, -1, -1, (mraa_pincapabilities_t){1,0,0,0, 0,0,0,0}, "GND"); + mraa_radxa_cm5_io_pininfo(b, 15, 4, 4, (mraa_pincapabilities_t){1,1,0,0,0,1,0,0}, "GPIO4_A4"); + mraa_radxa_cm5_io_pininfo(b, 16, 1, 20, (mraa_pincapabilities_t){1,1,1,0,1,1,0,0}, "GPIO1_C4"); + mraa_radxa_cm5_io_pininfo(b, 17, -1, -1, (mraa_pincapabilities_t){1,0,0,0, 0,0,0,0}, "3V3"); + mraa_radxa_cm5_io_pininfo(b, 18, 1, 29, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO1_D5"); + mraa_radxa_cm5_io_pininfo(b, 19, 4, 1, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO4_A1"); + mraa_radxa_cm5_io_pininfo(b, 20, -1, -1, (mraa_pincapabilities_t){1,0,0,0, 0,0,0,0}, "GND"); + mraa_radxa_cm5_io_pininfo(b, 21, 4, 0, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO4_A0"); + mraa_radxa_cm5_io_pininfo(b, 22, 1, 9, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO1_B1"); + mraa_radxa_cm5_io_pininfo(b, 23, 4, 2, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO4_A2"); + mraa_radxa_cm5_io_pininfo(b, 24, 4, 10, (mraa_pincapabilities_t){1,1,1,0,1,1,0,0}, "GPIO4_B2"); + mraa_radxa_cm5_io_pininfo(b, 25, -1, -1, (mraa_pincapabilities_t){1,0,0,0, 0,0,0,0}, "GND"); + mraa_radxa_cm5_io_pininfo(b, 26, 3, 15, (mraa_pincapabilities_t){1,1,0,0,1,1,0,0}, "GPIO3_B7"); + mraa_radxa_cm5_io_pininfo(b, 27, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3"); + mraa_radxa_cm5_io_pininfo(b, 28, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3"); + mraa_radxa_cm5_io_pininfo(b, 29, 0, 24, (mraa_pincapabilities_t){1,1,1,0,1,1,0,0}, "GPIO0_D0"); + mraa_radxa_cm5_io_pininfo(b, 30, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_cm5_io_pininfo(b, 31, 0, 23, (mraa_pincapabilities_t){1,1,1,0,1,1,0,0}, "GPIO0_C7"); + mraa_radxa_cm5_io_pininfo(b, 32, 1, 15, (mraa_pincapabilities_t){1,1,1,0,0,1,0,0}, "GPIO1_B7"); + mraa_radxa_cm5_io_pininfo(b, 33, 1, 17, (mraa_pincapabilities_t){1,1,0,0,1,1,0,1}, "GPIO1_C1"); + mraa_radxa_cm5_io_pininfo(b, 34, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_cm5_io_pininfo(b, 35, 3, 16, (mraa_pincapabilities_t){1,1,0,0,1,1,0,0}, "GPIO3_C0"); + mraa_radxa_cm5_io_pininfo(b, 36, 1, 22, (mraa_pincapabilities_t){1,1,1,0,0,1,0,0}, "GPIO1_C6"); + mraa_radxa_cm5_io_pininfo(b, 37, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,1,0}, "SARADC_VIN4"); + mraa_radxa_cm5_io_pininfo(b, 38, 1, 26, (mraa_pincapabilities_t){1,1,1,0,0,1,0,0}, "GPIO1_D2"); + mraa_radxa_cm5_io_pininfo(b, 39, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_cm5_io_pininfo(b, 40, 0, 27, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO0_D3"); + + return b; +}