diff --git a/README.md b/README.md index 2115869..87a66c5 100644 --- a/README.md +++ b/README.md @@ -47,6 +47,7 @@ ARM * [ADLINK IPi-SMARC ARM](../master/docs/adlink_ipi_arm.md) * [Radxa ROCK 3C](../master/docs/radxa_rock_3c.md) * [Radxa ROCK 5A](../master/docs/radxa_rock_5a.md) +* [Radxa ROCK 5B](../master/docs/radxa_rock_5b.md) * [Rock Pi 4](../master/docs/rockpi4.md) MIPS diff --git a/api/mraa/types.h b/api/mraa/types.h index 98c06c1..14b70c9 100644 --- a/api/mraa/types.h +++ b/api/mraa/types.h @@ -71,7 +71,8 @@ typedef enum { MRAA_SIEMENS_IOT2050 = 26, /**< Siemens IOT2050 board */ MRAA_RADXA_ROCK_3C = 27, /**< Radxa ROCK 3 Model C */ MRAA_VISIONFIVE = 28, /**< StarFive VisionFive board */ - MRAA_RADXA_ROCK_5A = 29, /**< Radxa ROCK 5 Model A */ + MRAA_RADXA_ROCK_5A = 29, /**< Radxa ROCK 5 Model A */ + MRAA_RADXA_ROCK_5B = 30, /**< Radxa ROCK 5 Model B */ // USB platform extenders start at 256 MRAA_FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */ @@ -213,6 +214,40 @@ typedef enum { MRAA_RADXA_ROCK_5A_PIN40 = 40 } mraa_radxa_rock_5a_wiring_t; +/** + * Radxa ROCK 5 Model B GPIO numbering enum + */ +typedef enum { + MRAA_RADXA_ROCK_5B_PIN3 = 3, + MRAA_RADXA_ROCK_5B_PIN5 = 5, + MRAA_RADXA_ROCK_5B_PIN7 = 7, + MRAA_RADXA_ROCK_5B_PIN8 = 8, + MRAA_RADXA_ROCK_5B_PIN10 = 10, + MRAA_RADXA_ROCK_5B_PIN11 = 11, + MRAA_RADXA_ROCK_5B_PIN12 = 12, + MRAA_RADXA_ROCK_5B_PIN13 = 13, + MRAA_RADXA_ROCK_5B_PIN15 = 15, + MRAA_RADXA_ROCK_5B_PIN16 = 16, + MRAA_RADXA_ROCK_5B_PIN18 = 18, + MRAA_RADXA_ROCK_5B_PIN19 = 19, + MRAA_RADXA_ROCK_5B_PIN21 = 21, + MRAA_RADXA_ROCK_5B_PIN22 = 22, + MRAA_RADXA_ROCK_5B_PIN23 = 23, + MRAA_RADXA_ROCK_5B_PIN24 = 24, + MRAA_RADXA_ROCK_5B_PIN26 = 26, + MRAA_RADXA_ROCK_5B_PIN27 = 27, + MRAA_RADXA_ROCK_5B_PIN28 = 28, + MRAA_RADXA_ROCK_5B_PIN29 = 29, + MRAA_RADXA_ROCK_5B_PIN31 = 31, + MRAA_RADXA_ROCK_5B_PIN32 = 32, + MRAA_RADXA_ROCK_5B_PIN33 = 33, + MRAA_RADXA_ROCK_5B_PIN35 = 35, + MRAA_RADXA_ROCK_5B_PIN36 = 36, + MRAA_RADXA_ROCK_5B_PIN37 = 37, + MRAA_RADXA_ROCK_5B_PIN38 = 38, + MRAA_RADXA_ROCK_5B_PIN40 = 40 +} mraa_radxa_rock_5b_wiring_t; + /** * Radxa ROCK 3 Model C GPIO numbering enum */ diff --git a/api/mraa/types.hpp b/api/mraa/types.hpp index d6629aa..1a464d6 100644 --- a/api/mraa/types.hpp +++ b/api/mraa/types.hpp @@ -66,6 +66,7 @@ typedef enum { RADXA_ROCK_3C = 27, /**< Radxa ROCK 3 Model C */ VISIONFIVE = 28, /**< StarFive VisionFive board */ RADXA_ROCK_5A = 29, /**< Radxa ROCK 5 Model A */ + RADXA_ROCK_5B = 30, /**< Radxa ROCK 5 Model B */ FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */ @@ -204,6 +205,40 @@ typedef enum { RADXA_ROCK_5A_PIN40 = 40 } RadxaRock5AWiring; +/** + * Radxa ROCK 5 Model B GPIO numbering enum + */ +typedef enum { + RADXA_ROCK_5B_PIN3 = 3, + RADXA_ROCK_5B_PIN5 = 5, + RADXA_ROCK_5B_PIN7 = 7, + RADXA_ROCK_5B_PIN8 = 8, + RADXA_ROCK_5B_PIN10 = 10, + RADXA_ROCK_5B_PIN11 = 11, + RADXA_ROCK_5B_PIN12 = 12, + RADXA_ROCK_5B_PIN13 = 13, + RADXA_ROCK_5B_PIN15 = 15, + RADXA_ROCK_5B_PIN16 = 16, + RADXA_ROCK_5B_PIN18 = 18, + RADXA_ROCK_5B_PIN19 = 19, + RADXA_ROCK_5B_PIN21 = 21, + RADXA_ROCK_5B_PIN22 = 22, + RADXA_ROCK_5B_PIN23 = 23, + RADXA_ROCK_5B_PIN24 = 24, + RADXA_ROCK_5B_PIN26 = 26, + RADXA_ROCK_5B_PIN27 = 27, + RADXA_ROCK_5B_PIN28 = 28, + RADXA_ROCK_5B_PIN29 = 29, + RADXA_ROCK_5B_PIN31 = 31, + RADXA_ROCK_5B_PIN32 = 32, + RADXA_ROCK_5B_PIN33 = 33, + RADXA_ROCK_5B_PIN35 = 35, + RADXA_ROCK_5B_PIN36 = 36, + RADXA_ROCK_5B_PIN37 = 37, + RADXA_ROCK_5B_PIN38 = 38, + RADXA_ROCK_5B_PIN40 = 40 +} RadxaRock5BWiring; + /** * Radxa ROCK 3 Model C GPIO numbering enum */ diff --git a/docs/radxa_rock_5b.md b/docs/radxa_rock_5b.md new file mode 100644 index 0000000..a7def12 --- /dev/null +++ b/docs/radxa_rock_5b.md @@ -0,0 +1,47 @@ +Radxa ROCK 5 Model B {#_Radxa} +==================== + +Radxa ROCK 5 Model B is a Rockchip RK3588 based SBC(Single Board Computer) by Radxa. It can run Android or Linux. Radxa ROCK 5 Model B features a four core ARM processor, 64bit dual channel 5500Mb/s LPDDR5, HDMI up to 8K60fps, MIPI DSI, MIPI CSI, 3.5mm combo audio jack, Wi-Fi 6, Bluetooth 5.0, USB, GbE LAN, and 40-pin color expansion header. Radxa ROCK 5 Model B is powered by the USB Type-C port, and supports 5V input only. The recommended power adapter is 5V/3A without SSD, or 5V/5A with SSD. + +Interface notes +--------------- + +- UART2 is enabled as the default console. +- All UART ports support baud up to 1500000. + +Pin Mapping +----------- + +Radxa ROCK 5 Model B has a 40-pin expansion header. Each pin is distinguished by the color. + +| Function5| Function4| Function3| Function2| Function1| PIN | PIN | Function1| Function2| Function3| Function4| +|-----------|-------------|-------------|-------------|-----------|:------|------:|----------|-------------|------------|------------| +| | | | | 3V3| 1 | 2 | +5.0V| | | | +| | | I2C7_SDA_M3| PWM15_IR_M1| GPIO4_B3| 3 | 4 | +5.0V| | | | +| | | I2C7_SCL_M3| PWM14_M1| GPIO4_B2| 5 | 6 | GND| | | | +|SPI1_CS1_M1| I2C8_SDA_M4|UART7_CTSN_M1| PWM15_IR_M0| GPIO3_C3| 7 | 8 | GPIO0_B5| UART2_TX_M0| I2C1_SCL_M0| | +| | | | | GND| 9 | 10 | GPIO0_B6| UART2_RX_M0| I2C1_SDA_M0| | +| | | SPI1_CLK_M1| UART7_RX_M1| GPIO3_C1| 11 | 12 | GPIO3_B5| PWM12_M0| UART3_TX_M1| | +| | | SPI1_MOSI_M1| I2C3_SCL_M1| GPIO3_B7| 13 | 14 | GND| | | | +| | UART7_TX_M1| SPI1_MISO_M1| I2C3_SDA_M1| GPIO3_C0| 15 | 16 | GPIO3_A4| UART4_RX_M1| | | +| | | | | +3.3V| 17 | 18 | GPIO4_C4| UART4_TX_M1| PWM5_M2| | +| | | UART4_RX_M2| SPI0_MOSI_M2| GPIO1_B2| 19 | 20 | GND| | | | +| | | PWM12_M1| SPI0_MISO_M2| GPIO1_B1| 21 | 22 |SARADC_IN4| | | | +| | | UART4_TX_M2| SPI0_CLK_M2| GPIO1_B3| 23 | 24 | GPIO1_B4| UART7_RX_M2| SPI0_CS0_M2| UART9_RX_M1| +| | | | | GND| 25 | 26 | GPIO1_B5| UART7_TX_M2| SPI0_CS1_M2| | +| | SPI3_CLK_M0| I2C0_SDA_M1| PWM7_IR_M3| GPIO4_C6| 27 | 28 | GPIO4_C5| |SPI3_MOSI_M0| | +| | | | PWM15_IR_M3| GPIO1_D7| 29 | 30 | GND| | | | +| | | | PWM13_M2| GPIO1_B7| 31 | 32 | GPIO3_C2| PWM14_M0| I2C8_SCL_M4| | +| | | | PWM8_M0| GPIO3_A7| 33 | 34 | GND| | | | +| | | UART3_RX_M1| PWM13_M0| GPIO3_B6| 35 | 36 | GPIO3_B1| PWM2_M1| UART2_TX_M2| | +| | | | | NC| 37 | 38 | GPIO3_B2| PWM3_IR_M1| UART2_RX_M2| | +| | | | | GND| 39 | 40 | GPIO3_B3| | | | + +Supports +-------- + +You can find additional product support in the following channels: + +- [Product Info](https://docs.radxa.com/en/rock5/rock5b) +- [Forums](https://forum.radxa.com/c/rock5) +- [Github](https://github.com/radxa) \ No newline at end of file diff --git a/include/arm/radxa_rock_5b.h b/include/arm/radxa_rock_5b.h new file mode 100644 index 0000000..bfedf8f --- /dev/null +++ b/include/arm/radxa_rock_5b.h @@ -0,0 +1,30 @@ +/* + * Author: Nascs + * Copyright (c) Radxa Limited. + * + * SPDX-License-Identifier: MIT + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "mraa_internal.h" + +#define MRAA_RADXA_ROCK_5B_GPIO_COUNT 26 +#define MRAA_RADXA_ROCK_5B_I2C_COUNT 4 +#define MRAA_RADXA_ROCK_5B_SPI_COUNT 2 +#define MRAA_RADXA_ROCK_5B_UART_COUNT 4 +#define MRAA_RADXA_ROCK_5B_PWM_COUNT 10 +#define MRAA_RADXA_ROCK_5B_AIO_COUNT 1 +#define MRAA_RADXA_ROCK_5B_PIN_COUNT 40 +#define PLATFORM_NAME_RADXA_ROCK_5B "Radxa ROCK 5B" + +mraa_board_t * + mraa_radxa_rock_5b(); + +#ifdef __cplusplus +} +#endif diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index fb308a0..0ae3df2 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -109,6 +109,7 @@ set (mraa_LIB_ARM_SRCS_NOAUTO ${PROJECT_SOURCE_DIR}/src/arm/de_nano_soc.c ${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_3c.c ${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_5a.c + ${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_5b.c ${PROJECT_SOURCE_DIR}/src/arm/rockpi4.c ${PROJECT_SOURCE_DIR}/src/arm/adlink_ipi.c ${PROJECT_SOURCE_DIR}/src/arm/siemens/iot2050.c diff --git a/src/arm/arm.c b/src/arm/arm.c index 5c271a3..54fea0b 100644 --- a/src/arm/arm.c +++ b/src/arm/arm.c @@ -12,6 +12,7 @@ #include "arm/96boards.h" #include "arm/radxa_rock_3c.h" #include "arm/radxa_rock_5a.h" +#include "arm/radxa_rock_5b.h" #include "arm/rockpi4.h" #include "arm/de_nano_soc.h" #include "arm/banana.h" @@ -97,6 +98,8 @@ mraa_arm_platform() platform_type = MRAA_RADXA_ROCK_3C; else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_ROCK_5A)) platform_type = MRAA_RADXA_ROCK_5A; + else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_ROCK_5B)) + platform_type = MRAA_RADXA_ROCK_5B; else if (mraa_file_contains("/proc/device-tree/model", "ROCK Pi 4") || mraa_file_contains("/proc/device-tree/model", "ROCK PI 4") || mraa_file_contains("/proc/device-tree/model", "ROCK 4") @@ -132,6 +135,9 @@ mraa_arm_platform() case MRAA_RADXA_ROCK_5A: plat = mraa_radxa_rock_5a(); break; + case MRAA_RADXA_ROCK_5B: + plat = mraa_radxa_rock_5b(); + break; case MRAA_ROCKPI4: plat = mraa_rockpi4(); break; diff --git a/src/arm/radxa_rock_5b.c b/src/arm/radxa_rock_5b.c new file mode 100644 index 0000000..a979509 --- /dev/null +++ b/src/arm/radxa_rock_5b.c @@ -0,0 +1,183 @@ +#include +#include +#include +#include +#include + +#include "arm/radxa_rock_5b.h" +#include "common.h" + +#define DT_BASE "/proc/device-tree" + +const char* radxa_rock_5b_serialdev[MRAA_RADXA_ROCK_5B_UART_COUNT] = { "/dev/ttyS2", "/dev/ttyS3", "/dev/ttyS4", "/dev/ttyS7"}; + +void +mraa_radxa_rock_5b_pininfo(mraa_board_t* board, int index, int gpio_chip, int gpio_line, mraa_pincapabilities_t pincapabilities_t, char* pin_name) +{ + if (index > board->phy_pin_count) + return; + + mraa_pininfo_t* pininfo = &board->pins[index]; + strncpy(pininfo->name, pin_name, MRAA_PIN_NAME_SIZE); + + if(pincapabilities_t.gpio == 1) { + pininfo->gpio.gpio_chip = gpio_chip; + pininfo->gpio.gpio_line = gpio_line; + } + + pininfo->capabilities = pincapabilities_t; + + pininfo->gpio.mux_total = 0; +} + +mraa_board_t* +mraa_radxa_rock_5b() +{ + mraa_board_t* b = (mraa_board_t*) calloc(1, sizeof(mraa_board_t)); + if (b == NULL) { + return NULL; + } + + b->adv_func = (mraa_adv_func_t*) calloc(1, sizeof(mraa_adv_func_t)); + if (b->adv_func == NULL) { + free(b); + return NULL; + } + + // pin mux for buses are setup by default by kernel so tell mraa to ignore them + b->no_bus_mux = 1; + b->phy_pin_count = MRAA_RADXA_ROCK_5B_PIN_COUNT + 1; + + // UART + b->uart_dev_count = MRAA_RADXA_ROCK_5B_UART_COUNT; + b->platform_name = PLATFORM_NAME_RADXA_ROCK_5B; + b->def_uart_dev = 0; + b->uart_dev[0].index = 2; + b->uart_dev[1].index = 3; + b->uart_dev[2].index = 4; + b->uart_dev[3].index = 7; + b->uart_dev[0].device_path = (char*) radxa_rock_5b_serialdev[0]; + b->uart_dev[1].device_path = (char*) radxa_rock_5b_serialdev[1]; + b->uart_dev[2].device_path = (char*) radxa_rock_5b_serialdev[2]; + b->uart_dev[3].device_path = (char*) radxa_rock_5b_serialdev[3]; + + // I2C + b->i2c_bus_count = MRAA_RADXA_ROCK_5B_I2C_COUNT; + b->def_i2c_bus = 0; + b->i2c_bus[0].bus_id = 0; + b->i2c_bus[1].bus_id = 1; + b->i2c_bus[2].bus_id = 3; + b->i2c_bus[3].bus_id = 8; + + // SPI + b->spi_bus_count = MRAA_RADXA_ROCK_5B_SPI_COUNT; + b->def_spi_bus = 0; + b->spi_bus[0].bus_id = 0; + b->spi_bus[1].bus_id = 1; + + b->pwm_dev_count = MRAA_RADXA_ROCK_5B_PWM_COUNT; + b->pwm_default_period = 500; + b->pwm_max_period = 2147483; + b->pwm_min_period = 1; + + b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t) * b->phy_pin_count); + if (b->pins == NULL) { + free(b->adv_func); + free(b); + return NULL; + } + + b->pins[36].pwm.parent_id = 2; // PWM2_M1 + b->pins[36].pwm.mux_total = 0; + b->pins[36].pwm.pinmap = 0; + b->pins[38].pwm.parent_id = 3; // PWM3_M1 + b->pins[38].pwm.mux_total = 0; + b->pins[38].pwm.pinmap = 0; + b->pins[18].pwm.parent_id = 5; // PWM5_M2 + b->pins[18].pwm.mux_total = 0; + b->pins[18].pwm.pinmap = 0; + b->pins[28].pwm.parent_id = 6; // PWM6_M2 + b->pins[28].pwm.mux_total = 0; + b->pins[28].pwm.pinmap = 0; + b->pins[27].pwm.parent_id = 7; // PWM7_M3 + b->pins[27].pwm.mux_total = 0; + b->pins[27].pwm.pinmap = 0; + b->pins[33].pwm.parent_id = 8; // PWM8_M0 + b->pins[33].pwm.mux_total = 0; + b->pins[33].pwm.pinmap = 0; + b->pins[12].pwm.parent_id = 12; // PWM12_M0 + b->pins[12].pwm.mux_total = 0; + b->pins[12].pwm.pinmap = 0; + b->pins[35].pwm.parent_id = 13; // PWM13_M0 + b->pins[35].pwm.mux_total = 0; + b->pins[35].pwm.pinmap = 0; + b->pins[31].pwm.parent_id = 13; // PWM13_M2 + b->pins[31].pwm.mux_total = 0; + b->pins[31].pwm.pinmap = 0; + b->pins[32].pwm.parent_id = 14; // PWM14_M0 + b->pins[32].pwm.mux_total = 0; + b->pins[32].pwm.pinmap = 0; + b->pins[5].pwm.parent_id = 14; // PWM14_M2 + b->pins[5].pwm.mux_total = 0; + b->pins[5].pwm.pinmap = 0; + b->pins[7].pwm.parent_id = 15; // PWM15_M0 + b->pins[7].pwm.mux_total = 0; + b->pins[7].pwm.pinmap = 0; + b->pins[3].pwm.parent_id = 15; // PWM15_M1 + b->pins[3].pwm.mux_total = 0; + b->pins[3].pwm.pinmap = 0; + b->pins[29].pwm.parent_id = 7; // PWM15_M3 + b->pins[29].pwm.mux_total = 0; + b->pins[29].pwm.pinmap = 0; + + b->aio_count = MRAA_RADXA_ROCK_5B_AIO_COUNT; + b->adc_raw = 10; + b->adc_supported = 10; + b->aio_dev[0].pin = 22; + b->aio_non_seq = 1; + b->chardev_capable = 1; + + mraa_radxa_rock_5b_pininfo(b, 0, -1, -1, (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, "INVALID"); + mraa_radxa_rock_5b_pininfo(b, 1, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3"); + mraa_radxa_rock_5b_pininfo(b, 2, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "5V"); + mraa_radxa_rock_5b_pininfo(b, 3, 4, 11, (mraa_pincapabilities_t){1,1,1,0,0,0,0,0}, "GPIO4_B3"); // i2c7 channel is occupied by i2c7-m0 in kernel + mraa_radxa_rock_5b_pininfo(b, 4, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "5V"); + mraa_radxa_rock_5b_pininfo(b, 5, 4, 10, (mraa_pincapabilities_t){1,1,1,0,0,0,0,0}, "GPIO4_B2"); // i2c7 channel is occupied by i2c7-m0 in kernel + mraa_radxa_rock_5b_pininfo(b, 6, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_5b_pininfo(b, 7, 3, 19, (mraa_pincapabilities_t){1,1,1,0,1,1,0,1}, "GPIO3_C3"); + mraa_radxa_rock_5b_pininfo(b, 8, 4, 13, (mraa_pincapabilities_t){1,0,0,0,0,1,0,1}, "GPIO0_B5"); // GPIO0_B5 was used by fiq_debugger, function GPIO cannot be enabled + mraa_radxa_rock_5b_pininfo(b, 9, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_5b_pininfo(b, 10, 0, 14, (mraa_pincapabilities_t){1,0,0,0,0,1,0,1}, "GPIO0_B6"); // GPIO0_B6 was used by fiq_debugger, function GPIO cannot be enabled + mraa_radxa_rock_5b_pininfo(b, 11, 3, 17, (mraa_pincapabilities_t){1,1,1,0,1,0,0,1}, "GPIO3_C1"); + mraa_radxa_rock_5b_pininfo(b, 12, 3, 13, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO3_B5"); + mraa_radxa_rock_5b_pininfo(b, 13, 3, 15, (mraa_pincapabilities_t){1,1,0,0,1,1,0,0}, "GPIO3_B7"); + mraa_radxa_rock_5b_pininfo(b, 14, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_5b_pininfo(b, 15, 3, 16, (mraa_pincapabilities_t){1,0,0,0,1,1,0,1}, "GPIO3_C0"); + mraa_radxa_rock_5b_pininfo(b, 16, 3, 4, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO3_A4"); + mraa_radxa_rock_5b_pininfo(b, 17, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3"); + mraa_radxa_rock_5b_pininfo(b, 18, 4, 20, (mraa_pincapabilities_t){1,1,1,0,1,0,0,0}, "GPIO4_C4"); + mraa_radxa_rock_5b_pininfo(b, 19, 1, 10, (mraa_pincapabilities_t){1,1,0,0,1,0,0,1}, "GPIO1_B2"); + mraa_radxa_rock_5b_pininfo(b, 20, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_5b_pininfo(b, 21, 1, 9, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO1_B1"); + mraa_radxa_rock_5b_pininfo(b, 22, -1, -1, (mraa_pincapabilities_t){1,0,0,0,1,0,1,0}, "SARADC_IN4"); + mraa_radxa_rock_5b_pininfo(b, 23, 1, 11, (mraa_pincapabilities_t){1,1,0,0,1,0,0,1}, "GPIO1_B3"); + mraa_radxa_rock_5b_pininfo(b, 24, 1, 12, (mraa_pincapabilities_t){1,1,0,0,1,0,0,1}, "GPIO1_B4"); + mraa_radxa_rock_5b_pininfo(b, 25, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_5b_pininfo(b, 26, 1, 13, (mraa_pincapabilities_t){1,1,0,0,1,0,0,1}, "GPIO1_B5"); + mraa_radxa_rock_5b_pininfo(b, 27, 4, 22, (mraa_pincapabilities_t){1,1,1,0,1,1,0,0}, "GPIO4_C6"); + mraa_radxa_rock_5b_pininfo(b, 28, 4, 21, (mraa_pincapabilities_t){1,1,1,0,1,1,0,0}, "GPIO4_C5"); + mraa_radxa_rock_5b_pininfo(b, 29, 1, 31, (mraa_pincapabilities_t){1,1,1,0,0,0,0,0}, "GPIO1_D7"); + mraa_radxa_rock_5b_pininfo(b, 30, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_5b_pininfo(b, 31, 1, 15, (mraa_pincapabilities_t){1,1,1,0,0,0,0,0}, "GPIO1_B7"); + mraa_radxa_rock_5b_pininfo(b, 32, 3, 18, (mraa_pincapabilities_t){1,1,1,0,1,1,0,1}, "GPIO3_C2"); + mraa_radxa_rock_5b_pininfo(b, 33, 3, 7, (mraa_pincapabilities_t){1,1,1,0,0,0,0,0}, "GPIO3_A7"); + mraa_radxa_rock_5b_pininfo(b, 34, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_5b_pininfo(b, 35, 3, 14, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO3_B6"); + mraa_radxa_rock_5b_pininfo(b, 36, 3, 9, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO3_B1"); + mraa_radxa_rock_5b_pininfo(b, 37, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,1,0}, "NC"); + mraa_radxa_rock_5b_pininfo(b, 38, 3, 10, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO3_B2"); + mraa_radxa_rock_5b_pininfo(b, 39, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_5b_pininfo(b, 40, 3, 11, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_B3"); + + return b; +}