diff --git a/README.md b/README.md index 7c5fc3d..3106225 100644 --- a/README.md +++ b/README.md @@ -46,6 +46,7 @@ ARM * [96Boards](../master/docs/96boards.md) * [ADLINK IPi-SMARC ARM](../master/docs/adlink_ipi_arm.md) * [Radxa CM3](../master/docs/radxa_cm3.md) +* [Radxa ROCK 3A](../master/docs/radxa_rock_3a.md) * [Radxa ROCK 3B](../master/docs/radxa_rock_3b.md) * [Radxa ROCK 3C](../master/docs/radxa_rock_3c.md) * [Radxa ROCK 5A](../master/docs/radxa_rock_5a.md) diff --git a/api/mraa/types.h b/api/mraa/types.h index 312ee0e..ea99d5a 100644 --- a/api/mraa/types.h +++ b/api/mraa/types.h @@ -77,6 +77,7 @@ typedef enum { MRAA_RADXA_ROCK_3B = 32, /**< Radxa ROCK 3 Model B */ MRAA_RADXA_CM3 = 33, /**< Radxa CM3 */ MRAA_RADXA_CM5_IO = 34, /**< Radxa CM5 IO */ + MRAA_RADXA_ROCK_3A = 35, /**< Radxa ROCK 3 Model A */ // USB platform extenders start at 256 MRAA_FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */ @@ -283,6 +284,40 @@ typedef enum { RADXA_CM5_IO_PIN40 = 40 } mraa_radxa_cm5_io_wiring_t; +/** + * Radxa ROCK 3 Model A GPIO numbering enum + */ +typedef enum { + MRAA_RADXA_ROCK_3A_PIN3 = 3, + MRAA_RADXA_ROCK_3A_PIN5 = 5, + MRAA_RADXA_ROCK_3A_PIN7 = 7, + MRAA_RADXA_ROCK_3A_PIN8 = 8, + MRAA_RADXA_ROCK_3A_PIN10 = 10, + MRAA_RADXA_ROCK_3A_PIN11 = 11, + MRAA_RADXA_ROCK_3A_PIN12 = 12, + MRAA_RADXA_ROCK_3A_PIN13 = 13, + MRAA_RADXA_ROCK_3A_PIN15 = 15, + MRAA_RADXA_ROCK_3A_PIN16 = 16, + MRAA_RADXA_ROCK_3A_PIN17 = 17, + MRAA_RADXA_ROCK_3A_PIN18 = 18, + MRAA_RADXA_ROCK_3A_PIN19 = 19, + MRAA_RADXA_ROCK_3A_PIN21 = 21, + MRAA_RADXA_ROCK_3A_PIN23 = 23, + MRAA_RADXA_ROCK_3A_PIN24 = 24, + MRAA_RADXA_ROCK_3A_PIN26 = 26, + MRAA_RADXA_ROCK_3A_PIN27 = 27, + MRAA_RADXA_ROCK_3A_PIN28 = 28, + MRAA_RADXA_ROCK_3A_PIN29 = 29, + MRAA_RADXA_ROCK_3A_PIN31 = 31, + MRAA_RADXA_ROCK_3A_PIN32 = 32, + MRAA_RADXA_ROCK_3A_PIN33 = 33, + MRAA_RADXA_ROCK_3A_PIN35 = 35, + MRAA_RADXA_ROCK_3A_PIN36 = 36, + MRAA_RADXA_ROCK_3A_PIN37 = 37, + MRAA_RADXA_ROCK_3A_PIN38 = 38, + MRAA_RADXA_ROCK_3A_PIN40 = 40 +} mraa_radxa_rock_3a_wiring_t; + /** * Radxa ROCK 3 Model B GPIO numbering enum */ diff --git a/api/mraa/types.hpp b/api/mraa/types.hpp index 41d281b..3449eb1 100644 --- a/api/mraa/types.hpp +++ b/api/mraa/types.hpp @@ -71,6 +71,7 @@ typedef enum { RADXA_ROCK_3B = 32, /**< Radxa ROCK 3 Model B */ RADXA_CM3 = 33, /**< Radxa CM3 */ RADXA_CM5_IO = 34, /**< Radxa CM5 IO */ + RADXA_ROCK_3A = 35, /**< Radxa ROCK 3 Model A */ FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */ @@ -274,6 +275,40 @@ typedef enum { RADXA_CM5_IO_PIN40 = 40 } RadxaCM5IOWiring; +/** + * Radxa ROCK 3 Model A GPIO numbering enum + */ +typedef enum { + RADXA_ROCK_3A_PIN3 = 3, + RADXA_ROCK_3A_PIN5 = 5, + RADXA_ROCK_3A_PIN7 = 7, + RADXA_ROCK_3A_PIN8 = 8, + RADXA_ROCK_3A_PIN10 = 10, + RADXA_ROCK_3A_PIN11 = 11, + RADXA_ROCK_3A_PIN12 = 12, + RADXA_ROCK_3A_PIN13 = 13, + RADXA_ROCK_3A_PIN15 = 15, + RADXA_ROCK_3A_PIN16 = 16, + RADXA_ROCK_3A_PIN17 = 17, + RADXA_ROCK_3A_PIN18 = 18, + RADXA_ROCK_3A_PIN19 = 19, + RADXA_ROCK_3A_PIN21 = 21, + RADXA_ROCK_3A_PIN23 = 23, + RADXA_ROCK_3A_PIN24 = 24, + RADXA_ROCK_3A_PIN26 = 26, + RADXA_ROCK_3A_PIN27 = 27, + RADXA_ROCK_3A_PIN28 = 28, + RADXA_ROCK_3A_PIN29 = 29, + RADXA_ROCK_3A_PIN31 = 31, + RADXA_ROCK_3A_PIN32 = 32, + RADXA_ROCK_3A_PIN33 = 33, + RADXA_ROCK_3A_PIN35 = 35, + RADXA_ROCK_3A_PIN36 = 36, + RADXA_ROCK_3A_PIN37 = 37, + RADXA_ROCK_3A_PIN38 = 38, + RADXA_ROCK_3A_PIN40 = 40 +} RadxaRock3AWiring; + /** * Radxa ROCK 3 Model B GPIO numbering enum */ diff --git a/docs/index.java.md b/docs/index.java.md index cee6243..dc942fc 100644 --- a/docs/index.java.md +++ b/docs/index.java.md @@ -56,6 +56,7 @@ Specific platform information for supported platforms is documented here: - @ref _orange_pi_prime - @ref radxa_cm3 - @ref radxa_cm5_io +- @ref radxa_rock_3a - @ref radxa_rock_3b - @ref radxa_rock_3c - @ref radxa_rock_5a diff --git a/docs/index.md b/docs/index.md index 7e9ae7c..6ea892d 100644 --- a/docs/index.md +++ b/docs/index.md @@ -64,6 +64,7 @@ Specific platform information for supported platforms is documented here: - @ref _orange_pi_prime - @ref radxa_cm3 - @ref radxa_cm5_io +- @ref radxa_rock_3a - @ref radxa_rock_3b - @ref radxa_rock_3c - @ref radxa_rock_5a diff --git a/docs/radxa_rock_3a.md b/docs/radxa_rock_3a.md new file mode 100644 index 0000000..ed4c712 --- /dev/null +++ b/docs/radxa_rock_3a.md @@ -0,0 +1,47 @@ +Radxa ROCK 3 Model A {#_Radxa} +==================== + +Radxa ROCK 3 Model A is a Rockchip RK3568 based SBC(Single Board Computer) by Radxa. It can run Android or Linux. Radxa ROCK 3 Model A features a four core ARM processor, 64bit dual channel 3200Mb/s LPDDR4, HDMI up to 4K60p, MIPI DSI, MIPI CSI, 3.5mm combo audio jack, Wi-Fi 6, Bluetooth 5.0, USB, GbE LAN, and 40-pin color expansion header. Radxa ROCK 3 Model A is powered by the USB Type-C port, and supports 5V input only. The recommended power adapter is 5V/3A without SSD, or 5V/5A with SSD. + +Interface notes +--------------- + +- UART2 is enabled as the default console. +- All UART ports support baud up to 1500000. + +Pin Mapping +----------- + +Radxa ROCK 3 Model A has a 40-pin expansion header. Each pin is distinguished by the color. + +| Function5| Function4| Function3| Function2| Function1| PIN | PIN | Function1| Function2| Function3| Function4| Function5| +|-------------|-------------|-----------|-------------|-----------|:------|------:|----------|-------------|-----------|------------|------------| +| | | | | 3V3| 1 | 2 |+5.0V | | | | | +| | |UART3_RX_M0| I2C3_SDA_M0| GPIO1_A0| 3 | 4 |+5.0V | | | | | +| | |UART3_TX_M0| I2C3_SCL_M0| GPIO1_A1| 5 | 6 |GND | |UART2_TXD | | | +| | PWM1_M1| | I2C2_SCL_M0| GPIO0_B5| 7 | 8 |GPIO0_D1 | |UART2_RXD | | | +| | | | | GND| 9 | 10 |GPIO0_D0 | | | | | +| | PWM14_M0|UART7_TX_M1| | GPIO3_C4| 11 | 12 |GPIO3_A3 | | | | | +| | PWM15_IR_M0|UART7_RX_M1| | GPIO3_C5| 13 | 14 |GND | | | | | +| | PWM1_M0| UART0_RX| | GPIO0_C0| 15 | 16 |GPIO0_B6 |I2C2_SDA_M0 | |PWM2_M1 | | +| | | | | 3V3| 17 | 18 |GPIO3_B2 | |UART4_TX_M1| | | +| SPI3_MOSI_M1| PWM15_IR_M1| | | GPIO4_C3| 19 | 20 |GND | | | | | +| SPI3_MISO_M1| PWM12_M1|UART9_TX_M1| | GPIO4_C5| 21 | 22 |GPIO0_C1 | |UART0_TX |PWM2_M0 | | +| SPI3_CLK_M1| PWM14_M1| | | GPIO4_C2| 23 | 24 |GPIO4_C6 | |UART9_RX_M1|PWM13_M1 |SPI3_CS0_M1 | +| | | | | GND| 25 | 26 |GPIO4_D1 | | | |SPI3_CS1_M1 | +| | PWM2_M1| | I2C1_SDA| GPIO0_B4| 27 | 28 |GPIO0_B3 |I2C1_SCL | |PWM1_M1 | | +| | |UART8_TX_M1| | GPIO2_D7| 29 | 30 |GND | | | | | +| SPI2_CLK_M1| |UART8_RX_M1| | GPIO3_A0| 31 | 32 |GPIO3_C2 | |UART5_TX_M1| | | +| | |UART5_RX_M1| | GPIO3_C3| 33 | 34 |GND | | | | | +| | | | | GPIO3_A4| 35 | 36 |GPIO3_A2 | | | | | +| | | | |SARADC_VIN5| 37 | 38 |GPIO3_A6 | | | | | +| | | | | GND| 39 | 40 |GPIO3_A5 | | | | | + +Supports +-------- + +You can find additional product support in the following channels: + +- [Product Info](https://docs.radxa.com/en/rock3/rock3a) +- [Forums](https://forum.radxa.com/c/rock3) +- [Github](https://github.com/radxa) diff --git a/include/arm/radxa_rock_3a.h b/include/arm/radxa_rock_3a.h new file mode 100644 index 0000000..e71d5d2 --- /dev/null +++ b/include/arm/radxa_rock_3a.h @@ -0,0 +1,30 @@ +/* + * Author: Nascs + * Copyright (c) Radxa Limited. + * + * SPDX-License-Identifier: MIT + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "mraa_internal.h" + +#define MRAA_RADXA_ROCK_3A_GPIO_COUNT 28 +#define MRAA_RADXA_ROCK_3A_I2C_COUNT 3 +#define MRAA_RADXA_ROCK_3A_SPI_COUNT 1 +#define MRAA_RADXA_ROCK_3A_UART_COUNT 7 +#define MRAA_RADXA_ROCK_3A_PWM_COUNT 11 +#define MRAA_RADXA_ROCK_3A_AIO_COUNT 1 +#define MRAA_RADXA_ROCK_3A_PIN_COUNT 40 +#define PLATFORM_NAME_RADXA_ROCK_3A "Radxa ROCK3 Model A" + +mraa_board_t * + mraa_radxa_rock_3a(); + +#ifdef __cplusplus +} +#endif diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 273c4be..200d8ae 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -107,6 +107,7 @@ set (mraa_LIB_ARM_SRCS_NOAUTO ${PROJECT_SOURCE_DIR}/src/arm/phyboard.c ${PROJECT_SOURCE_DIR}/src/arm/banana.c ${PROJECT_SOURCE_DIR}/src/arm/de_nano_soc.c + ${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_3a.c ${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_3b.c ${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_3c.c ${PROJECT_SOURCE_DIR}/src/arm/radxa_cm3.c diff --git a/src/arm/arm.c b/src/arm/arm.c index ccc5839..d859e80 100644 --- a/src/arm/arm.c +++ b/src/arm/arm.c @@ -11,6 +11,7 @@ #include "arm/96boards.h" #include "arm/radxa_cm3.h" +#include "arm/radxa_rock_3a.h" #include "arm/radxa_rock_3b.h" #include "arm/radxa_rock_3c.h" #include "arm/radxa_rock_5a.h" @@ -102,6 +103,8 @@ mraa_arm_platform() mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_CM3_IO_2) || mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_CM3_RPI_CM4_IO)) platform_type = MRAA_RADXA_CM3; + else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_ROCK_3A)) + platform_type = MRAA_RADXA_ROCK_3A; else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_ROCK_3B)) platform_type = MRAA_RADXA_ROCK_3B; else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_ROCK_3C)) @@ -146,6 +149,9 @@ mraa_arm_platform() case MRAA_RADXA_CM3: plat = mraa_radxa_cm3(); break; + case MRAA_RADXA_ROCK_3A: + plat = mraa_radxa_rock_3a(); + break; case MRAA_RADXA_ROCK_3B: plat = mraa_radxa_rock_3b(); break; diff --git a/src/arm/radxa_rock_3a.c b/src/arm/radxa_rock_3a.c new file mode 100644 index 0000000..a409f72 --- /dev/null +++ b/src/arm/radxa_rock_3a.c @@ -0,0 +1,169 @@ +/* + * Author: Nascs + * Copyright (c) Radxa Limited. + * + * SPDX-License-Identifier: MIT + */ + +#include +#include +#include +#include +#include +#include "arm/radxa_rock_3a.h" +#include "common.h" + +const char* radxa_rock_3a_serialdev[MRAA_RADXA_ROCK_3A_UART_COUNT] = { "/dev/ttyS0", "/dev/ttyS2", "/dev/ttyS3", "/dev/ttyS5", "/dev/ttyS7", "/dev/ttyS8", "/dev/ttyS9" }; + +void +mraa_radxa_rock_3a_pininfo(mraa_board_t* board, int index, int gpio_chip, int gpio_line, mraa_pincapabilities_t pincapabilities_t, char* pin_name) +{ + + if (index > board->phy_pin_count) + return; + + mraa_pininfo_t* pininfo = &board->pins[index]; + strncpy(pininfo->name, pin_name, MRAA_PIN_NAME_SIZE); + + if(pincapabilities_t.gpio == 1) { + pininfo->gpio.gpio_chip = gpio_chip; + pininfo->gpio.gpio_line = gpio_line; + } + + pininfo->capabilities = pincapabilities_t; + + pininfo->gpio.mux_total = 0; +} + +mraa_board_t* +mraa_radxa_rock_3a() +{ + mraa_board_t* b = (mraa_board_t*) calloc(1, sizeof(mraa_board_t)); + if (b == NULL) { + return NULL; + } + + b->adv_func = (mraa_adv_func_t*) calloc(1, sizeof(mraa_adv_func_t)); + if (b->adv_func == NULL) { + free(b); + return NULL; + } + + // pin mux for buses are setup by default by kernel so tell mraa to ignore them + b->no_bus_mux = 1; + b->phy_pin_count = MRAA_RADXA_ROCK_3A_PIN_COUNT + 1; + + b->platform_name = PLATFORM_NAME_RADXA_ROCK_3A; + b->chardev_capable = 1; + + // UART + b->uart_dev_count = MRAA_RADXA_ROCK_3A_UART_COUNT; + b->def_uart_dev = 0; + b->uart_dev[0].index = 0; + b->uart_dev[1].index = 2; + b->uart_dev[2].index = 3; + b->uart_dev[3].index = 5; + b->uart_dev[4].index = 7; + b->uart_dev[5].index = 8; + b->uart_dev[6].index = 9; + b->uart_dev[0].device_path = (char*) radxa_rock_3a_serialdev[0]; + b->uart_dev[1].device_path = (char*) radxa_rock_3a_serialdev[1]; + b->uart_dev[2].device_path = (char*) radxa_rock_3a_serialdev[2]; + b->uart_dev[3].device_path = (char*) radxa_rock_3a_serialdev[3]; + b->uart_dev[4].device_path = (char*) radxa_rock_3a_serialdev[4]; + b->uart_dev[5].device_path = (char*) radxa_rock_3a_serialdev[5]; + b->uart_dev[6].device_path = (char*) radxa_rock_3a_serialdev[6]; + + // I2C + b->i2c_bus_count = MRAA_RADXA_ROCK_3A_I2C_COUNT; + b->def_i2c_bus = 0; + b->i2c_bus[0].bus_id = 1; + b->i2c_bus[1].bus_id = 2; + b->i2c_bus[2].bus_id = 3; + + // SPI + b->spi_bus_count = MRAA_RADXA_ROCK_3A_SPI_COUNT; + b->def_spi_bus = 0; + b->spi_bus[0].bus_id = 3; + + // PWM + b->pwm_dev_count = MRAA_RADXA_ROCK_3A_PWM_COUNT; + b->pwm_default_period = 500; + b->pwm_max_period = 2147483; + b->pwm_min_period = 1; + + b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t) * b->phy_pin_count); + if (b->pins == NULL) { + free(b->adv_func); + free(b); + return NULL; + } + + b->pins[7].pwm.parent_id = 12; // PWM12_M0 + b->pins[7].pwm.mux_total = 0; + b->pins[11].pwm.parent_id = 14; // PWM14_M0 + b->pins[11].pwm.mux_total = 0; + b->pins[13].pwm.parent_id = 15; // PWM15_IR_M0 + b->pins[13].pwm.mux_total = 0; + b->pins[15].pwm.parent_id = 1; // PWM1_M0 + b->pins[15].pwm.mux_total = 0; + b->pins[19].pwm.parent_id = 15; // PWM15_IR_M1 + b->pins[19].pwm.mux_total = 0; + b->pins[21].pwm.parent_id = 12; // PWM12_M1 + b->pins[21].pwm.mux_total = 0; + b->pins[23].pwm.parent_id = 14; // PWM14_M1 + b->pins[23].pwm.mux_total = 0; + b->pins[24].pwm.parent_id = 13; // PWM13_M1 + b->pins[24].pwm.mux_total = 0; + b->pins[18].pwm.parent_id = 9; // PWM9_M0 + b->pins[18].pwm.mux_total = 0; + b->pins[16].pwm.parent_id = 2; // PWM2_M1 + b->pins[16].pwm.mux_total = 0; + b->pins[7].pwm.parent_id = 1; // PWM1_M1 + b->pins[7].pwm.mux_total = 0; + + // hardware V1.3/V1.31 + mraa_radxa_rock_3a_pininfo(b, 0, -1, -1, (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, "INVALID"); + mraa_radxa_rock_3a_pininfo(b, 1, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3"); + mraa_radxa_rock_3a_pininfo(b, 2, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "5V"); + mraa_radxa_rock_3a_pininfo(b, 3, 1, 0, (mraa_pincapabilities_t){1,1,0,0,0,1,0,1}, "GPIO1_A0"); + mraa_radxa_rock_3a_pininfo(b, 4, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "5V"); + mraa_radxa_rock_3a_pininfo(b, 5, 1, 1, (mraa_pincapabilities_t){1,1,0,0,0,1,0,1}, "GPIO1_A1"); + mraa_radxa_rock_3a_pininfo(b, 6, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_3a_pininfo(b, 7, 0, 13, (mraa_pincapabilities_t){1,1,1,0,0,1,0,0}, "GPIO0_B5"); + mraa_radxa_rock_3a_pininfo(b, 8, 1, 24, (mraa_pincapabilities_t){1,0,0,0,0,0,0,1}, "GPIO0_D1"); // GPIO0_D1 was used by fiq_debugger, function GPIO cannot be enabled + mraa_radxa_rock_3a_pininfo(b, 9, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_3a_pininfo(b, 10, 1, 25, (mraa_pincapabilities_t){1,0,0,0,0,0,0,1}, "GPIO0_D1"); // GPIO0_D0 was used by fiq_debugger, function GPIO cannot be enabled + mraa_radxa_rock_3a_pininfo(b, 11, 3, 20, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO3_C4"); + mraa_radxa_rock_3a_pininfo(b, 12, 3, 3, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_A3"); + mraa_radxa_rock_3a_pininfo(b, 13, 3, 21, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO3_C5"); + mraa_radxa_rock_3a_pininfo(b, 14, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_3a_pininfo(b, 15, 0, 16, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO0_C0"); + mraa_radxa_rock_3a_pininfo(b, 16, 3, 1, (mraa_pincapabilities_t){1,1,1,0,0,1,0,0}, "GPIO0_B6"); + mraa_radxa_rock_3a_pininfo(b, 17, -1, -1, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "+3.3V"); + mraa_radxa_rock_3a_pininfo(b, 18, 3, 10, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO3_B2"); + mraa_radxa_rock_3a_pininfo(b, 19, 4, 19, (mraa_pincapabilities_t){1,1,1,0,1,0,0,0}, "GPIO4_C3"); + mraa_radxa_rock_3a_pininfo(b, 20, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_3a_pininfo(b, 21, 4, 21, (mraa_pincapabilities_t){1,1,1,0,1,0,0,1}, "GPIO4_C5"); + mraa_radxa_rock_3a_pininfo(b, 22, 0, 17, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO0_C1"); + mraa_radxa_rock_3a_pininfo(b, 23, 4, 18, (mraa_pincapabilities_t){1,1,1,0,1,0,0,0}, "GPIO4_C2"); + mraa_radxa_rock_3a_pininfo(b, 24, 4, 22, (mraa_pincapabilities_t){1,1,1,0,1,0,0,1}, "GPIO4_C6"); + mraa_radxa_rock_3a_pininfo(b, 25, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_3a_pininfo(b, 26, 4, 25, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO4_D1"); + mraa_radxa_rock_3a_pininfo(b, 27, 0, 14, (mraa_pincapabilities_t){1,1,0,0,0,1,0,0}, "GPIO0_B4"); // Hardware pull-up on this pin + mraa_radxa_rock_3a_pininfo(b, 28, 0, 13, (mraa_pincapabilities_t){1,1,0,0,0,1,0,0}, "GPIO0_B3"); // Hardware pull-up on this pin + mraa_radxa_rock_3a_pininfo(b, 29, 2, 31, (mraa_pincapabilities_t){1,1,0,0,0,0,0,1}, "GPIO2_D7"); + mraa_radxa_rock_3a_pininfo(b, 30, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_3a_pininfo(b, 31, 3, 0, (mraa_pincapabilities_t){1,1,0,0,1,0,0,1}, "GPIO3_A0"); + mraa_radxa_rock_3a_pininfo(b, 32, 3, 18, (mraa_pincapabilities_t){1,1,0,0,0,0,0,1}, "GPIO3_C2"); + mraa_radxa_rock_3a_pininfo(b, 33, 3, 19, (mraa_pincapabilities_t){1,1,0,0,1,0,0,1}, "GPIO3_C3"); + mraa_radxa_rock_3a_pininfo(b, 34, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_3a_pininfo(b, 35, 3, 4, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_A4"); + mraa_radxa_rock_3a_pininfo(b, 36, 3, 2, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_A2"); + mraa_radxa_rock_3a_pininfo(b, 37, 3, 16, (mraa_pincapabilities_t){1,0,0,0,0,0,1,0}, "SARADC_VIN5"); + mraa_radxa_rock_3a_pininfo(b, 38, 3, 6, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_A6"); + mraa_radxa_rock_3a_pininfo(b, 39, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND"); + mraa_radxa_rock_3a_pininfo(b, 40, 3, 5, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_A5"); + + return b; +}