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up: add support for UP Board

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Add support for UP board (www.up-board.org), scoping
the following functions available via 40-pin header:
* GPIO (via sysfs)
* UART
* I2C
* SPI
* PWM

Validated on UP board v0.2, running ubilinux 3.0

Signed-off-by: Dan O'Donovan <dan@emutex.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
This commit is contained in:
Dan O'Donovan
2016-02-24 14:25:54 +00:00
committed by Brendan Le Foll
parent 3b2a5b8429
commit f9501c5c78
10 changed files with 352 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
README.md
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@@ -23,6 +23,7 @@ X86
* [Intel DE3815](../master/docs/intel_de3815.md) * [Intel DE3815](../master/docs/intel_de3815.md)
* [Minnowboard Max](../master/docs/minnow_max.md) * [Minnowboard Max](../master/docs/minnow_max.md)
* [NUC 5th generation](../master/docs/intel_nuc5.md) * [NUC 5th generation](../master/docs/intel_nuc5.md)
* [UP](../master/docs/up.md)
ARM ARM
--- ---

1
api/mraa/types.h
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@@ -49,6 +49,7 @@ typedef enum {
MRAA_96BOARDS = 9, /**< Linaro 96boards */ MRAA_96BOARDS = 9, /**< Linaro 96boards */
MRAA_INTEL_SOFIA_3GR = 10, /**< The Intel SoFIA 3GR */ MRAA_INTEL_SOFIA_3GR = 10, /**< The Intel SoFIA 3GR */
MRAA_INTEL_CHERRYHILLS = 11, /**< The Intel Braswell Cherryhills */ MRAA_INTEL_CHERRYHILLS = 11, /**< The Intel Braswell Cherryhills */
MRAA_UP = 12, /**< The UP Board */
// USB platform extenders start at 256 // USB platform extenders start at 256
MRAA_FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */ MRAA_FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */

1
docs/index.md
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@@ -46,6 +46,7 @@ Specific platform information for supported platforms is documented here:
- @ref bananapi - @ref bananapi
- @ref beaglebone - @ref beaglebone
- @ref nuc5 - @ref nuc5
- @ref up
- @ref ft4222 - @ref ft4222
## DEBUGGING ## DEBUGGING

84
docs/up.md Normal file
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@@ -0,0 +1,84 @@
UP Board {#up}
============
UP Board is based on the Intel(R) Atom(TM) x5-Z83xx SoC (formerly Cherry Trail).
It includes 2GB RAM, 16/32GB eMMC flash, 6 USB2.0 ports, 1 USB 3.0 OTG port,
1 Gigabit Ethernet, HDMI and DSI Graphics ports, RTC and a 40-pin I/O header.
The form-factor for the board is based on the Raspberry Pi 2, and can be used
with many of the add-on HAT boards designed for the Raspberry Pi 2.
Interface notes
---------------
**PWM** PWM frequency range is from 293 Hz to 6.4 MHz. 8-bit resolution is
supported for duty-cycle adjustments, but this reduces for frequencies > 97.6kHz
**I2C** 2 I2C channels support standard-mode (100kHz) and fast-mode (400kHz).
Bus frequency can be selected in BIOS settings. Note that, unlike Raspberry Pi,
the I2C controller issues Repeated-START commands for combined transactions
(e.g. a write-then-read transaction) which may not be supported by some I2C
slave devices. For such devices, it is advisable to use separate write and
read transactions to ensure that Repeated-STARTs are not issued.
**SPI** Bus frequencies up to 25MHz are supported, in steps which are less
granular at higher speeds. E.g. Available speeds include:
25MHz, 12.5MHz, 8.33MHz, 6.25MHz, 5MHz, 4.167MHz, 3.571MHz, 3.125MHz, etc.
Please be aware that speeds in between those steps will be rounded UP to the
next nearest available speed, and capped at 25MHz.
At the time of writing, only a single native chip-select is available (SPI CS0).
**UART** 2 high-speed UARTs are available, supporting baud rates up to
support baud rates between 300 and 3686400. Hardware flow-control signals are
not exposed, so software flow-control may be needed for rates above 115200.
A console UART is also available but is not fully supported at this time.
Pin Mapping
-----------
The GPIO numbering in the following pin mapping is based on the Raspberry Pi
model 2 and B+ numbering scheme.
Note that there is an enum to use wiringPi style numbers.
| MRAA Number | Physical Pin | Function | Sysfs GPIO | Notes |
|-------------|--------------|----------|------------|----------------------|
| 1 | P1-01 | 3V3 VCC | | |
| 2 | P1-02 | 5V VCC | | |
| 3 | P1-03 | I2C SDA1 | 2 | I2C1 (/dev/i2c-1) |
| 4 | P1-04 | 5V VCC | | |
| 5 | P1-05 | I2C SCL1 | 3 | I2C1 (/dev/i2c-1) |
| 6 | P1-06 | GND | | |
| 7 | P1-07 | GPIO(4) | 4 | |
| 8 | P1-08 | UART TX1 | 14 | UART1 (/dev/ttyS1) |
| 9 | P1-09 | GND | | |
| 10 | P1-10 | UART RX1 | 15 | UART1 (/dev/ttyS1) |
| 11 | P1-11 | GPIO(17) | 17 | |
| 12 | P1-12 | I2S CLK | 18 | I2S0 (PCM Audio) |
| 13 | P1-13 | UART RX2 | 27 | UART2 (/dev/ttyS2) |
| 14 | P1-14 | GND | | |
| 15 | P1-15 | GPIO(22) | 22 | |
| 16 | P1-16 | GPIO(23) | 23 | |
| 17 | P1-17 | 3V3 VCC | | |
| 18 | P1-18 | GPIO(24) | 24 | |
| 19 | P1-19 | SPI MOSI | 10 | SPI2 (/dev/spidev2.x)|
| 20 | P1-20 | GND | | |
| 21 | P1-21 | SPI MISO | 9 | SPI2 (/dev/spidev2.x)|
| 22 | P1-22 | UART TX2 | 25 | UART2 (/dev/ttyS2) |
| 23 | P1-23 | SPI SCL | 11 | SPI2 (/dev/spidev2.x)|
| 24 | P1-24 | SPI CS0 | 8 | SPI2 (/dev/spidev2.0)|
| 25 | P1-25 | GND | | |
| 26 | P1-26 | SPI CS1 | 7 | SPI2 (/dev/spidev2.1)|
| 27 | P1-27 | I2C SDA0 | 0 | I2C0 (/dev/i2c-0) |
| 28 | P1-28 | I2C SCL0 | 1 | I2C0 (/dev/i2c-0) |
| 29 | P1-29 | GPIO(5) | 5 | |
| 30 | P1-30 | GND | | |
| 31 | P1-31 | GPIO(6) | 6 | |
| 32 | P1-32 | PWM0 | 12 | PWM Chip 0 Channel 0 |
| 33 | P1-33 | PWM1 | 13 | PWM Chip 1 Channel 0 |
| 34 | P1-34 | GND | | |
| 35 | P1-35 | I2S FRM | 19 | I2S0 (PCM Audio) |
| 36 | P1-36 | GPIO(16) | 16 | |
| 37 | P1-37 | GPIO(26) | 26 | |
| 38 | P1-38 | I2S DIN | 20 | I2S0 (PCM Audio) |
| 39 | P1-39 | GND | | |
| 40 | P1-40 | I2S DOUT | 21 | I2S0 (PCM Audio) |

1
examples/mraa-i2c.c
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@@ -73,6 +73,7 @@ print_bus(mraa_board_t* board)
case MRAA_RASPBERRY_PI: case MRAA_RASPBERRY_PI:
case MRAA_BEAGLEBONE: case MRAA_BEAGLEBONE:
case MRAA_BANANA: case MRAA_BANANA:
case MRAA_UP:
bus = i; bus = i;
busType = "linux"; busType = "linux";
break; break;

43
include/x86/up.h Normal file
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@@ -0,0 +1,43 @@
/*
* Author: Dan O'Donovan <dan@emutex.com>
* Copyright (c) 2015 Emutex Ltd.
* Copyright (c) 2014 Intel Corporation.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "mraa_internal.h"
// +1 as pins are "1 indexed"
#define MRAA_UP_PINCOUNT (40 + 1)
#define MRAA_UP_GPIOCOUNT (28)
mraa_board_t*
mraa_up_board();
#ifdef __cplusplus
}
#endif

1
src/CMakeLists.txt
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@@ -29,6 +29,7 @@ set (mraa_LIB_X86_SRCS_NOAUTO
${PROJECT_SOURCE_DIR}/src/x86/intel_minnow_byt_compatible.c ${PROJECT_SOURCE_DIR}/src/x86/intel_minnow_byt_compatible.c
${PROJECT_SOURCE_DIR}/src/x86/intel_sofia_3gr.c ${PROJECT_SOURCE_DIR}/src/x86/intel_sofia_3gr.c
${PROJECT_SOURCE_DIR}/src/x86/intel_cherryhills.c ${PROJECT_SOURCE_DIR}/src/x86/intel_cherryhills.c
${PROJECT_SOURCE_DIR}/src/x86/up.c
) )
message (INFO " - Adding support for platform ${MRAAPLATFORMFORCE}") message (INFO " - Adding support for platform ${MRAAPLATFORMFORCE}")

1
src/python/docs/index.rst
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@@ -28,6 +28,7 @@ Supported Platforms
* `Banana Pi/Pro <../bananapi.html>`_ * `Banana Pi/Pro <../bananapi.html>`_
* `Beaglebone Black <../beaglebone.html>`_ * `Beaglebone Black <../beaglebone.html>`_
* `Intel NUC NUC5i5MYBE <../nuc5.html>`_ * `Intel NUC NUC5i5MYBE <../nuc5.html>`_
* `UP <../up.html>`_
* `FTDI FT4222H <../ft4222.html>`_ * `FTDI FT4222H <../ft4222.html>`_
Compiling & Debugging libmraa Compiling & Debugging libmraa

215
src/x86/up.c Normal file
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@@ -0,0 +1,215 @@
/*
* Author: Dan O'Donovan <dan@emutex.com>
* Copyright (c) 2015 Emutex Ltd.
* Copyright (c) 2014 Intel Corporation.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <stdlib.h>
#include <string.h>
#include <sys/utsname.h>
#include <ctype.h>
#include "common.h"
#include "x86/up.h"
#define PLATFORM_NAME "UP"
#define I2C_BUS_DEFAULT 1
#define MAX_LENGTH 8
#define I2CNAME "designware"
static mraa_result_t
set_pininfo(mraa_board_t* board, int mraa_index, char* name, mraa_pincapabilities_t caps, int sysfs_pin)
{
if (mraa_index < board->phy_pin_count) {
mraa_pininfo_t* pin_info = &board->pins[mraa_index];
strncpy(pin_info->name, name, MAX_LENGTH);
pin_info->capabilites = caps;
if (caps.gpio) {
pin_info->gpio.pinmap = sysfs_pin;
pin_info->gpio.mux_total = 0;
}
if (caps.i2c) {
pin_info->i2c.pinmap = 1;
pin_info->i2c.mux_total = 0;
}
if (caps.pwm) {
int controller = 0;
if (strncmp(name, "PWM", 3) == 0 && strlen(name) > 3 && isdigit(name[3]))
controller = name[3] - '0';
pin_info->pwm.parent_id = controller;
pin_info->pwm.pinmap = 0;
pin_info->pwm.mux_total = 0;
}
if (caps.spi) {
pin_info->spi.mux_total = 0;
}
return MRAA_SUCCESS;
}
return MRAA_ERROR_INVALID_RESOURCE;
}
static mraa_result_t
get_pin_index(mraa_board_t* board, char* name, int* pin_index)
{
int i;
for (i = 0; i < board->phy_pin_count; ++i) {
if (strncmp(name, board->pins[i].name, MAX_LENGTH) == 0) {
*pin_index = i;
return MRAA_SUCCESS;
}
}
return MRAA_ERROR_INVALID_RESOURCE;
}
mraa_board_t*
mraa_up_board()
{
mraa_board_t* b = (mraa_board_t*) calloc(1, sizeof(mraa_board_t));
struct utsname running_uname;
int uname_major, uname_minor, max_pins[27];
if (b == NULL) {
return NULL;
}
b->platform_name = PLATFORM_NAME;
b->phy_pin_count = MRAA_UP_PINCOUNT;
b->gpio_count = MRAA_UP_GPIOCOUNT;
b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t) * MRAA_UP_PINCOUNT);
if (b->pins == NULL) {
goto error;
}
b->adv_func = (mraa_adv_func_t*) calloc(1, sizeof(mraa_adv_func_t));
if (b->adv_func == NULL) {
free(b->pins);
goto error;
}
if (uname(&running_uname) != 0) {
free(b->pins);
free(b->adv_func);
goto error;
}
sscanf(running_uname.release, "%d.%d", &uname_major, &uname_minor);
set_pininfo(b, 0, "INVALID", (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }, -1);
set_pininfo(b, 1, "3.3v", (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }, -1);
set_pininfo(b, 2, "5v", (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }, -1);
set_pininfo(b, 3, "I2C1_SDA", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 1, 0, 0 }, 2);
set_pininfo(b, 4, "5v", (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }, -1);
set_pininfo(b, 5, "I2C1_SCL", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 1, 0, 0 }, 3);
set_pininfo(b, 6, "GND", (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }, -1);
set_pininfo(b, 7, "GPIO4", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }, 4);
set_pininfo(b, 8, "UART1_TX", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 1 }, 14);
set_pininfo(b, 9, "GND", (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }, -1);
set_pininfo(b, 10, "UART1_RX", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 1 }, 15);
set_pininfo(b, 11, "GPIO17", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }, 17);
set_pininfo(b, 12, "I2S_CLK", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }, 18);
set_pininfo(b, 13, "UART2_RX", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 1, 0, 1 }, 27);
set_pininfo(b, 14, "GND", (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }, -1);
set_pininfo(b, 15, "GPIO22", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 1, 0, 0 }, 22);
set_pininfo(b, 16, "GPIO23", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }, 23);
set_pininfo(b, 17, "3.3v", (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }, -1);
set_pininfo(b, 18, "GPIO24", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }, 24);
set_pininfo(b, 19, "SPI_MOSI", (mraa_pincapabilities_t){ 1, 1, 0, 0, 1, 0, 0, 0 }, 10);
set_pininfo(b, 20, "GND", (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }, -1);
set_pininfo(b, 21, "SPI_MISO", (mraa_pincapabilities_t){ 1, 1, 0, 0, 1, 0, 0, 0 }, 9);
set_pininfo(b, 22, "UART2_TX", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 1 }, 25);
set_pininfo(b, 23, "SPI_CLK", (mraa_pincapabilities_t){ 1, 1, 0, 0, 1, 0, 0, 0 }, 11);
set_pininfo(b, 24, "SPI_CS0", (mraa_pincapabilities_t){ 1, 1, 0, 0, 1, 0, 0, 0 }, 8);
set_pininfo(b, 25, "GND", (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }, -1);
set_pininfo(b, 26, "SPI_CS1", (mraa_pincapabilities_t){ 1, 1, 0, 0, 1, 0, 0, 0 }, 7);
set_pininfo(b, 27, "ID_SD", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 1, 0, 0 }, 0);
set_pininfo(b, 28, "ID_SC", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 1, 0, 0 }, 1);
set_pininfo(b, 29, "GPIO5", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }, 5);
set_pininfo(b, 30, "GND", (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }, -1);
set_pininfo(b, 31, "GPIO6", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }, 6);
set_pininfo(b, 32, "PWM0", (mraa_pincapabilities_t){ 1, 1, 1, 0, 0, 0, 0, 0 }, 12);
set_pininfo(b, 33, "PWM1", (mraa_pincapabilities_t){ 1, 1, 1, 0, 0, 0, 0, 0 }, 13);
set_pininfo(b, 34, "GND", (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }, -1);
set_pininfo(b, 35, "I2S_FRM", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }, 19);
set_pininfo(b, 36, "GPIO16", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }, 16);
set_pininfo(b, 37, "GPIO26", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }, 26);
set_pininfo(b, 38, "I2S_DIN", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }, 20);
set_pininfo(b, 39, "GND", (mraa_pincapabilities_t){ 0, 0, 0, 0, 0, 0, 0, 0 }, -1);
set_pininfo(b, 40, "I2S_DOUT", (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 }, 21);
// Set number of i2c adaptors usable from userspace
b->i2c_bus_count = 2;
// Configure i2c adaptor #0 (default)
// (For consistency with Raspberry Pi 2, use I2C1 as our primary I2C bus)
b->i2c_bus[0].bus_id = 1;
get_pin_index(b, "I2C1_SDA", &(b->i2c_bus[0].sda));
get_pin_index(b, "I2C1_SCL", &(b->i2c_bus[0].scl));
// Configure i2c adaptor #1
// (normally reserved for accessing HAT EEPROM)
b->i2c_bus[1].bus_id = 0;
get_pin_index(b, "I2C0_SDA", &(b->i2c_bus[1].sda));
get_pin_index(b, "I2C0_SCL", &(b->i2c_bus[1].scl));
b->def_i2c_bus = 0;
// Configure PWM
b->pwm_default_period = 500;
b->pwm_max_period = 3413;
b->pwm_min_period = 1;
// Configure SPI #0 CS0 (default)
b->spi_bus_count = 2;
b->spi_bus[0].bus_id = 2;
b->spi_bus[0].slave_s = 0;
get_pin_index(b, "SPI_CS0", &(b->spi_bus[0].cs));
get_pin_index(b, "SPI_MOSI", &(b->spi_bus[0].mosi));
get_pin_index(b, "SPI_MISO", &(b->spi_bus[0].miso));
get_pin_index(b, "SPI_CLK", &(b->spi_bus[0].sclk));
b->def_spi_bus = 0;
// Configure SPI #0 CS1
b->spi_bus[1].bus_id = 2;
b->spi_bus[1].slave_s = 1;
get_pin_index(b, "SPI_CS1", &(b->spi_bus[1].cs));
get_pin_index(b, "SPI_MOSI", &(b->spi_bus[1].mosi));
get_pin_index(b, "SPI_MISO", &(b->spi_bus[1].miso));
get_pin_index(b, "SPI_CLK", &(b->spi_bus[1].sclk));
// Configure UART #1 (default)
b->uart_dev_count = 2;
get_pin_index(b, "UART1_RX", &(b->uart_dev[0].rx));
get_pin_index(b, "UART1_TX", &(b->uart_dev[0].tx));
b->uart_dev[0].device_path = "/dev/ttyS1";
b->def_uart_dev = 0;
// Configure UART #2
get_pin_index(b, "UART2_RX", &(b->uart_dev[1].rx));
get_pin_index(b, "UART2_TX", &(b->uart_dev[1].tx));
b->uart_dev[1].device_path = "/dev/ttyS2";
return b;
error:
syslog(LOG_CRIT, "up: Platform failed to initialise");
free(b);
return NULL;
}

4
src/x86/x86.c
View File

@@ -36,6 +36,7 @@
#include "x86/intel_minnow_byt_compatible.h" #include "x86/intel_minnow_byt_compatible.h"
#include "x86/intel_sofia_3gr.h" #include "x86/intel_sofia_3gr.h"
#include "x86/intel_cherryhills.h" #include "x86/intel_cherryhills.h"
#include "x86/up.h"
mraa_platform_t mraa_platform_t
mraa_x86_platform() mraa_x86_platform()
@@ -82,6 +83,9 @@ mraa_x86_platform()
} else if (strncasecmp(line, "Braswell Cherry Hill", 20) == 0) { } else if (strncasecmp(line, "Braswell Cherry Hill", 20) == 0) {
platform_type = MRAA_INTEL_CHERRYHILLS; platform_type = MRAA_INTEL_CHERRYHILLS;
plat = mraa_intel_cherryhills(); plat = mraa_intel_cherryhills();
} else if (strncasecmp(line, "UP-CHT01", 8) == 0) {
platform_type = MRAA_UP;
plat = mraa_up_board();
} else { } else {
syslog(LOG_ERR, "Platform not supported, not initialising"); syslog(LOG_ERR, "Platform not supported, not initialising");
platform_type = MRAA_UNKNOWN_PLATFORM; platform_type = MRAA_UNKNOWN_PLATFORM;