nuc5: Add i2c support for intel 5th generation NUC

Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>

README.md

@@ -22,6 +22,7 @@ X86
 * [Edison](../master/docs/edison.md)
 * [Intel DE3815](../master/docs/intel_de3815.md)
 * [Minnowboard Max](../master/docs/minnow_max.md)
+* [NUC 5th generation](../master/docs/intel_nuc5.md)
 
 ARM
 ---

api/mraa/types.h

@@ -45,6 +45,7 @@ typedef enum {
     MRAA_RASPBERRY_PI = 5,          /**< The different Raspberry PI Models -like  A,B,A+,B+ */
     MRAA_BEAGLEBONE = 6,            /**< The different BeagleBone Black Modes B/C */
     MRAA_BANANA = 7,                /**< Allwinner A20 based Banana Pi and Banana Pro */
+    MRAA_INTEL_NUC5 = 8,            /**< The Intel 5th generations Broadwell NUCs */
 
     MRAA_UNKNOWN_PLATFORM =
     99 /**< An unknown platform type, typically will load INTEL_GALILEO_GEN1 */

docs/index.md

@@ -45,6 +45,7 @@ Specific platform information for supported platforms is documented here:
 - @ref rasppi
 - @ref bananapi
 - @ref beaglebone
+- @ref nuc5
 
 ## DEBUGGING
 

docs/intel_nuc5.md

@@ -0,0 +1,46 @@
+Intel NUC NUC5i5MYBE                             {#nuc5}
+====================
+
+Pinmuxing on the 5th generation Intel NUCs is done in the BIOS. This is only
+tested on bios 0024+ (MYBDWi5v.86A). By default the custom solution header is
+disabled, currently in Linux (as of 4.2). Both i2c buses are currently
+supported.
+
+The NUCs supported are the NUC5i5MYBE & NUC5i3MYBE which also come as the
+NUC5i5MYHE and NUC5i3MYHE motherboards. It's possible that others expose the IO
+in a very similar way so could be supported, get in touch if you have one!
+
+In the BIOS you are required to enable the following:
+Devices -> Onboard Devices - GPIO Lockdown
+Select I2c under GPIO for the 12/13 14/15 pins
+
+Interface notes
+---------------
+
+**I2C** Depending on your system you may need to load `i2c-dev`
+
+Custom Solutions Header mapping
+-------------------------------
+
+The mapping is the same as the DE3815tykhe.
+
+| MRAA Number | Physical Pin | Function     | Notes                |
+|-------------|--------------|--------------|----------------------|
+| 0           | 1            | 1.8V sby     |                      |
+| 1           | 2            | GND          |                      |
+| 2           | 3            | HDMI_CEC     |                      |
+| 3           | 4            | DMIC_CLK     |                      |
+| 4           | 5            | 3.3V sby     |                      |
+| 5           | 6            | DMIC_DATA    |                      |
+| 6           | 7            | Key (no pin) |                      |
+| 7           | 8            | SMB_ALERT#   |                      |
+| 8           | 9            | 5V sby (2A)  |                      |
+| 9           | 10           | SCI_SMI_GPIO |                      |
+| 10          | 11           | PWM[0]       |                      |
+| 11          | 12           | PWM[1]       |                      |
+| 12          | 13           | I2C0_CLK     | /dev/i2c-0 SCL       |
+| 13          | 14           | I2C0_DATA    | /dev/i2c-0 SDA       |
+| 14          | 15           | I2C1_CLK     | /dev/i2c-1 SCL       |
+| 15          | 16           | I2C1_DATA    | /dev/i2c-1-SDA       |
+| 16          | 17           | SMB_CLK      |                      |
+| 17          | 18           | SMB_DATA     |                      |

include/x86/intel_nuc5.h

@@ -0,0 +1,40 @@
+/*
+ * Author: Brendan Le Foll <brendan.le.foll@intel.com>
+ * Copyright (c) 2015 Intel Corporation.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mraa_internal.h"
+
+#define MRAA_INTEL_NUC5_PINCOUNT 18
+
+mraa_board_t*
+mraa_intel_nuc5();
+
+#ifdef __cplusplus
+}
+#endif

src/CMakeLists.txt

@@ -24,6 +24,7 @@ set (mraa_LIB_X86_SRCS_NOAUTO
   ${PROJECT_SOURCE_DIR}/src/x86/intel_galileo_rev_g.c
   ${PROJECT_SOURCE_DIR}/src/x86/intel_edison_fab_c.c
   ${PROJECT_SOURCE_DIR}/src/x86/intel_de3815.c
+  ${PROJECT_SOURCE_DIR}/src/x86/intel_nuc5.c
   ${PROJECT_SOURCE_DIR}/src/x86/intel_minnow_max.c
 )
 

src/x86/intel_nuc5.c

@@ -0,0 +1,147 @@
+/*
+ * Author: Brendan Le Foll <brendan.le.foll@intel.com>
+ * Copyright (c) 2015 Intel Corporation.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+
+#include "common.h"
+#include "x86/intel_nuc5.h"
+
+#define PLATFORM_NAME "Intel NUC5"
+#define SYSFS_CLASS_GPIO "/sys/class/gpio"
+#define I2CNAME "designware"
+
+mraa_board_t*
+mraa_intel_nuc5()
+{
+    mraa_board_t* b = (mraa_board_t*) malloc(sizeof(mraa_board_t));
+    if (b == NULL) {
+        return NULL;
+    }
+
+    b->platform_name = PLATFORM_NAME;
+    b->phy_pin_count = MRAA_INTEL_NUC5_PINCOUNT;
+    b->aio_count = 0;
+    b->adc_raw = 0;
+    b->adc_supported = 0;
+    b->pwm_default_period = 0;
+    b->pwm_max_period = 0;
+    b->pwm_min_period = 0;
+
+    b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t) * MRAA_INTEL_NUC5_PINCOUNT);
+    if (b->pins == NULL) {
+        goto error;
+    }
+
+    strncpy(b->pins[0].name, "1.8v", 8);
+    b->pins[0].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
+
+    strncpy(b->pins[1].name, "GND", 8);
+    b->pins[1].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
+    strncpy(b->pins[2].name, "HDMIcec", 8);
+    b->pins[2].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
+    strncpy(b->pins[3].name, "DMICclk", 8);
+    b->pins[3].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
+    strncpy(b->pins[4].name, "3.3v", 8);
+    b->pins[4].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
+    strncpy(b->pins[5].name, "DMICda", 8);
+    b->pins[5].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
+    strncpy(b->pins[6].name, "Key", 8);
+    b->pins[6].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
+    strncpy(b->pins[7].name, "SMB-A", 8);
+    b->pins[7].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
+    strncpy(b->pins[8].name, "5v", 8);
+    b->pins[8].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
+    strncpy(b->pins[9].name, "SCI", 8);
+    b->pins[9].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
+
+    strncpy(b->pins[10].name, "PWM0", 8);
+    b->pins[10].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
+    b->pins[10].pwm.pinmap = 0;
+    b->pins[10].pwm.parent_id = 0;
+    b->pins[10].pwm.mux_total = 0;
+
+    strncpy(b->pins[11].name, "PWM1", 8);
+    b->pins[11].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
+    b->pins[11].pwm.pinmap = 0;
+    b->pins[11].pwm.parent_id = 1;
+    b->pins[11].pwm.mux_total = 0;
+
+    strncpy(b->pins[12].name, "I2C0SCL", 8);
+    b->pins[12].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 1, 0, 0 };
+    b->pins[12].i2c.pinmap = 1;
+    b->pins[12].i2c.mux_total = 0;
+
+    strncpy(b->pins[13].name, "I2C0SDA", 8);
+    b->pins[13].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 1, 0, 0 };
+    b->pins[13].i2c.pinmap = 1;
+    b->pins[13].i2c.mux_total = 0;
+
+    strncpy(b->pins[14].name, "I2C1SCL", 8);
+    b->pins[14].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 1, 0, 0 };
+    b->pins[14].i2c.pinmap = 1;
+    b->pins[14].i2c.mux_total = 0;
+
+    strncpy(b->pins[15].name, "I2C1SDA", 8);
+    b->pins[15].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 1, 0, 0 };
+    b->pins[15].i2c.pinmap = 1;
+    b->pins[15].i2c.mux_total = 0;
+
+    strncpy(b->pins[16].name, "SMB_CLK", 8);
+    b->pins[16].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
+    strncpy(b->pins[17].name, "SMB_SDA", 8);
+    b->pins[17].capabilites = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
+
+    b->i2c_bus_count = 0;
+    int i2c_num = -1;
+    int i;
+    for (i = 0; i < 2; i++) {
+        i2c_num = mraa_find_i2c_bus(I2CNAME, i2c_num + 1);
+        if (i2c_num == -1) {
+            break;
+        }
+        b->i2c_bus_count++;
+        b->i2c_bus[i].bus_id = i2c_num;
+        b->i2c_bus[i].sda = 12 + i;
+        b->i2c_bus[i].scl = 13 + i;
+    }
+
+    if (b->i2c_bus_count > 0) {
+        b->def_i2c_bus = b->i2c_bus[0].bus_id;
+    }
+
+
+    b->spi_bus_count = 0;
+    b->def_spi_bus = 0;
+    b->uart_dev_count = 0;
+
+    return b;
+error:
+    syslog(LOG_CRIT, "nuc5: Platform failed to initialise");
+    free(b);
+    return NULL;
+}

src/x86/x86.c

@@ -31,6 +31,7 @@
 #include "x86/intel_edison_fab_c.h"
 #include "x86/intel_de3815.h"
 #include "x86/intel_minnow_max.h"
+#include "x86/intel_nuc5.h"
 
 mraa_platform_t
 mraa_x86_platform()
@@ -54,6 +55,9 @@ mraa_x86_platform()
             } else if (strncmp(line, "DE3815", 6) == 0) {
                 platform_type = MRAA_INTEL_DE3815;
                 plat = mraa_intel_de3815();
+            } else if (strncmp(line, "NUC5i5MYBE", 10) == 0 || strncmp(line, "NUC5i3MYBE", 10) == 0) {
+                platform_type = MRAA_INTEL_NUC5;
+                plat = mraa_intel_nuc5();
             } else if (strncmp(line, "NOTEBOOK", 8) == 0) {
                 platform_type = MRAA_INTEL_MINNOWBOARD_MAX;
                 plat = mraa_intel_minnow_max();