GPIO and I2C functions of some PINs are not possible
with default BIOS configuration. Current documentation
wrongly shows that the PINs can work as both GPIO and I2C.
This patch fixes this issue and also updated pin conf for
I2C 1 and 2 to disable GPIO functionality.
Signed-off-by: Arun Ravindran <arun.ravindran@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
The earlier patches did not fix the following issues.
1) gpio number used for ISH I2C 0 and I2C 1 were not correct
2) gpio number used in ISH I2C 1 and I2C 2 were not correct
3) ISH UART 0 gpio numbers were wrong
This patch fixes this issue and also update the doc.
Signed-off-by: Arun Ravindran <arun.ravindran@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
MRAA is using gpio 484, 483, 485 and 486 as ISH UART1.
But J13 expansion connector doesn't expose ISH UART1,
instead it exposes ISH UART0 as per dev kit hardware guide.
This patch fixes this descrpency and renames the UART and
also enables the GPIO usage.
Signed-off-by: Arun Ravindran <arun.ravindran@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
The GPIOs are not mapped correctly in MRAA for tuchuk board.
This patch corrects the GPIO maps and the PIN assignments.
Note:
1) There are nothing called I2S(x)SDO and I2S(x)SDI available over breakout
pins, the usage is commented now.
2) There is nothing called SPP0FS3, is now commented, what we have is SPP1FS3.
3) I2C1SDA available twise 15 and 71. PIN 71 as per gpio used should be renamed as ISHI2C0SDA
4) I2C1SCL available twise 17 and 73. PIN 73 as per gpio used should be renamed as ISHI2C0SCL
5) UART1TX available twise 22 and 74. PIN 74 as per gpio used is ISHUART1TXD
and is not available in breakout.
6) UART1RX available twise 24 and 76. PIN 76 as per gpio used is ISHUART1RXD
and is not available in breakout.
7) I2C2SDA available twise 19 and 75. PIN 75 as per gpio used is ISHI2C1SDA
and is not available in breakout pins
8) I2C2SCL available twise 21 and 77. PIN 75 as per gpio used is ISHI2C1SCL
and is not available in breakout pins
9) PIN 78 UART1RT as per GPIO used is ISHUART1RT and is not available in breakout pins
10) PIN 80 UART1CT as per GPIO is ISHUART1CT and is not available in breakout pins
BIOS used is 193
Signed-off-by: Arun Ravindran <arun.ravindran@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
GT/GrosseTete -> Joule. This commit deprecates the MRAA_INTEL_GT_TUCHUCK
mraa_platform_t value and links the grossetete.md page to joule.md.
Signed-off-by: Wai Lun Poon <wai.lun.poon@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
