Calling mraa_intel_edison_misc_spi() is not really needed, because the
GPIO 10..13 pins will be configured correctly when the user actually
inits them as GPIO pins. When using these pins for GPIO,
mraa_setup_mux_mapped() and mraa_intel_edison_gpio_init_post() will do
all this work based on the pin map and pinmodes for the Edison Arduino
board.
On the contrary, this function would break any user of the SPI bus
that is already running.
Signed-off-by: Jonas Norling <jonas.norling@connode.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
There are technically two i2c buses that are user accesible on minnowboard max
but the other one is on the high speed expansion header that I've never tested
and it's not mapped in mraa so leave this to 1 until someone enables it.
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
Fixes#251. default_i2c_bus was set to 7 before setting actual parameters for
it leading to obvious failure as 0 != 7
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
NPM builds don't support cross compiling and will always compile for the host.
Binding.gyp now uses mraa_NPM_SRCS instead of mraa_LIB_SRCS_NOAUTO which
contains all platforms. Cmake now uses mraa_LIB_PLAT_SRCS_NOAUTO to provide all
the sources. NPM builds will build objects for all platforms reguardless of
space which does meann slightly bigger binaries.
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
Edison SPI driver doesn't support LSB_FIRST mode, we will now return
_FEATURE_NOT_SUPPORTED instead of _INVALID_RESOURCE
for attempts to enable it.
Closes#22.
Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
Galileo Gen1 doesn't support LSB_FIRST mode, so let's
return MRAA_ERROR_FEATURE_NOT_SUPPORTED instead of <...>_INVALID_RESOURCE.
Closes#178.
Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
Gpio 111 controls the use of hardware CS by the edison kernel's SPI driver.
This is an issue as that CS will go high between every byte transmitted. The
solution is to let gpio 111 alone and let the driver decide what is best. This
fixes#137
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
This reworks the mraa_intel_edison_i2c_freq() function. i2c_dw_sysnode is a
folder not a file so we need to grab the mode file from that folder. We now
also support i2c-1 frequency changing
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
This stops the legacy beahviour that was to initialise as a gen1 galileo if we
failed to find a valid dmi name. Closes#142
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
Not defining this causes undefined behaviour leading to the check mux_total
sometimes being true and asking the kernel to export all sorts of garbage gpio
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
Instead of plain char* to avoid need to malloc and do all the needed
error checking needed that goes along with that.
Signed-off-by: Thomas Ingleby <thomas.c.ingleby@intel.com>
Used for getting the path to the character device under linux for uart
device. i.e. "/dev/ttyS0"
Adds paths to existing platforms.
Closes#84
Signed-off-by: Thomas Ingleby <thomas.c.ingleby@intel.com>
Since gpios are +256 in 3.18+ kernels this stops dual definitions and possible
issues later on if errors are found
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
Whilst this value is not used because it's only required by the aio module it
is interesting to have this information if we want to expose it to the user
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
This should adjust the pinouts, at runtime, based on the current
kernel that's in use. The Linux kernel made a change between
3.17 and 3.18 ( specifically ea584595fc85e65796335033dfca25ed655cd0ed )
that changed the numbering for GPIOs. This obviously breaks everything
for mraa on the MinnowBoard MAX if you have a 3.18 or newer kernel.
Signed-off-by: John 'Warthog9' Hawley <john.hawley@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
The gpio_close_pre was put on the wrong board definition. So calling close of
GPIO pin on mini-board caused a fault
Signed-off-by: Kurt Eckhardt <kurte@rockisland.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
Made like changes to Edison to cache the output enable.
Note: different than Edison as the pin structure holds enable pin number
instead of external array.
2nd note: noticed PU resistors are also in structure but there is also
external array.
Signed-off-by: Kurt Eckhardt <kurte@rockisland.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
