UP Xtreme is based on the Intel(R) Core(TM) i3/i5/i7 Whiskey Lake SoCs.
The UP Xtreme presents one Raspberry Pi compatible HAT connector.
This implementaion supports i2c, spi, uart, adc and gpio through the
40pin HAT connector.
Gpio chardev capabilities have been disabled in this implementation. When
gpio chardev capabilities are enabled an input becomes unreadable after an
isr has been registered to the pin. See here for details:
https://github.com/intel-iot-devkit/mraa/issues/937
Tested on UP Xtreme, with UP Board Linux kernel 5.0.0
Features tested: gpio, gpio interrupts, i2c, spi, adc and uart.
Signed-off-by: Michael Campion <michael.campion@emutex.com>
* Use docker images from docker hub instead of building them on Travis
* Fix doxygen warnings for C/C++ Documentation
* Fix examples inclusion in documentation
* Modify Travis build matrix to include stages and additional jobs
* Update doxygen2jsdoc submodule
* Add doxyport submodule
* Generate documentation for each language in Travis
* Add sonar.java.binaries to sonar-scan.sh
Signed-off-by: Nicolas Oliver <dario.n.oliver@intel.com>
GT/GrosseTete -> Joule. This commit deprecates the MRAA_INTEL_GT_TUCHUCK
mraa_platform_t value and links the grossetete.md page to joule.md.
Signed-off-by: Wai Lun Poon <wai.lun.poon@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
Like the beaglebone, the phyBOARD-Wega also got an am335x.
So I merged the four mmap-functions for gpio_context and some
identical defines in a separate header and c-file.
The new platform support-files are based on beaglebone-files.
The documentation of phyBOARD-Wega is still in process,
but for now there are enough informations.
At this time it is possible to use GPIO-Pins and Uart0
(tested via python with mraa). The code for using SPI, I2C and
PWM is also still in process and not tested yet.
Signed-off-by: Norbert Wesp <nwesp@phytec.de>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
