Private
Public Access
2
0
Commit Graph

1194 Commits

Author SHA1 Message Date
Jandrioli
d74b0d8a73 Fix code to set SPI frequency/clock
Signed-off-by: Jandrioli <joao_andrioli@hotmail.com>
2020-09-15 10:38:37 -07:00
akgnah
710106d99f rockpi4: add model c support
Signed-off-by: akgnah <1024@setq.me>
2020-09-15 10:38:03 -07:00
Jefferson Lee
da36b7ae84 Added the mraa_strresult function
Signed-off-by: Jefferson Lee <jeffersonlee2000@gmail.com>
2020-09-15 10:37:05 -07:00
gowtham.r
68e75edcad Adding alias name LEC-ALAI for LEC-AL-AI platform.
Signed-off-by: gowtham.r <gowtham.r@adlinktech.com>
2020-09-15 10:36:11 -07:00
gowtham.r
52d1d93d00 Changed serial port address in ARM platform, chenged the spritnf call to snprintf call for safty reason. fixed other warnings.
Signed-off-by: gowtham.r <gowtham.r@adlinktech.com>
2020-09-15 10:36:11 -07:00
Chuckduey
c10e72b494 Added V1.2 for Pi 4 2GB and 4GB
Signed-off-by: Chuckduey <cduey@msn.com>
2020-05-07 13:36:03 -07:00
Chuck Duey
f58cdc9da4 Added Raspberry Pi 4 1GB 2GB and 4GB to the list of detected platforms
Signed-off-by: Chuck Duey <cduey@msn.com>
2020-01-10 09:33:19 -08:00
kathaashok
bb736e762b fixing indentation issues reported by eclipse mraa
Signed-off-by: kathaashok <katha.ashok@adlinktech.com>
2020-01-10 07:33:18 -08:00
katha ashok
ef8c0fb541 Fixing minor issues. supporting LEC-AL-AI board
Signed-off-by: katha ashok <katha.ashok@adlinktech.com>
2020-01-10 07:33:18 -08:00
Brian Lee
63de2c4c3a rockpi4.c: fixed pwm issue
e.g.:
    cv2 import at the beginning throws the error:
    import cv2
    import mraa
    import time
    ...

    Error:
    ValueError: Error initialising PWM on pin

Signed-off-by: Brian Lee <brian@vamrs.com>
2020-01-09 10:11:58 -08:00
Michael Campion
1d18da9a22 upxtreme: add spdx tags to source files
Remove MIT notice and replace with SPDX tags in UP Xtreme sources.

Signed-off-by: Michael Campion <michael.campion@emutex.com>
2020-01-06 15:17:55 +00:00
Michael Campion
d954599045 upxtreme: Add UP Xtreme support
UP Xtreme is based on the Intel(R) Core(TM) i3/i5/i7 Whiskey Lake SoCs.
The UP Xtreme presents one Raspberry Pi compatible HAT connector.

This implementaion supports i2c, spi, uart, adc and gpio through the
40pin HAT connector.

Gpio chardev capabilities have been disabled in this implementation. When
gpio chardev capabilities are enabled an input becomes unreadable after an
isr has been registered to the pin. See here for details:

https://github.com/intel-iot-devkit/mraa/issues/937

Tested on UP Xtreme, with UP Board Linux kernel 5.0.0
Features tested: gpio, gpio interrupts, i2c, spi, adc and uart.

Signed-off-by: Michael Campion <michael.campion@emutex.com>
2020-01-06 15:17:55 +00:00
Carsten Menke
79043568dd made Rock Pi 4 working again with recent 5.x kernels
Signed-off-by: Carsten Menke <cm@p-i-u.de>
2019-12-29 20:14:42 +00:00
gowtham.r
4ba5da1144 adding Adlink IPi SMARC x86/ARM support
Signed-off-by: gowtham.r <gowtham.r@adlinktech.com>
2019-12-03 07:52:58 -08:00
Benxi Liu
3b2f80b6e2 uart: fix xonxoff value in mraa_uart_settings()
the value of xonxoff(IXON|IXOFF) resides in the c_iflag field in
struct termios, not c_cflag.

Signed-off-by: Benxi Liu <bxliu@linux.alibaba.com>
2019-12-03 07:52:58 -08:00
Thomas Ingleby
c1eeb8ab87 eclipse: change Java namespace
io.mraa -> org.eclipse.mraa

Signed-off-by: Thomas Ingleby <thomas.ingleby@intel.com>
2019-11-13 13:14:20 -08:00
Thomas Ingleby
170bdd104f spdx: add spdx tags to most files
Large change that removes the duplicated MIT notice withe a spdx tag

Signed-off-by: Thomas Ingleby <thomas.ingleby@intel.com>
2019-05-23 10:09:12 -07:00
Manivannan Sadhasivam
0a12c5a017 gpio: Introduce mraa_gpio_init_by_name API
This commit introduces mraa_gpio_init_by_name API for initializing
a GPIO by its line name provided by the kernel. This feature depends
on the GPIO chardev support and also the line names present in devicetree
or board files. Accessing GPIO using its line name, removes the dependency
from MRAA specific pin mapping and provides a cleaner way to access GPIOs.
This will solve the issue created by an external gpiochip probing before
the SoC's internal gpio controller and thereby making the MRAA pin mapping
wrong.

Currently, this API only supports initializing a single GPIO at a time.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-05-10 16:29:13 +05:30
Manivannan Sadhasivam
111e6be8f7 96boards: Add chardev support to Rock960
Add chardev support to Rock960 96Boards.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-05-10 16:24:41 +05:30
Brian Lee
b8349c0ffe rockpi4: Add rockpi4 support
Closes #958

Signed-off-by: Brian Lee <brian@vamrs.com>
Signed-off-by: Thomas Ingleby <thomas.ingleby@intel.com>
2019-03-28 13:09:46 -07:00
Mihai Tudor Panu
8942117b2e x86.c: add missing platform init call when MRAAPLATFORMFORCE is set to IEI Tank
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2019-03-26 22:17:25 -07:00
Mihai Tudor Panu
7f8d3876e3 clang-format: reapply to recently modified sources
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2019-03-06 13:14:09 -08:00
Cosmin Popescu
41fc378099 initio.c: Fix for null pointer passed as parameter
Signed-off-by: Cosmin Popescu <gabrielcosmin.popescu@gmail.com>
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2019-03-06 12:13:01 -08:00
Cosmin Popescu
c821c19899 mraa:c Fix dereference of null pointer
Signed-off-by: Cosmin Popescu <gabrielcosmin.popescu@gmail.com>
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2019-03-06 12:12:52 -08:00
Cosmin Popescu
89473e5ba4 gpio.c: Add fix for closing of uninitialzed fds
Signed-off-by: Cosmin Popescu <gabrielcosmin.popescu@gmail.com>
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2019-03-06 12:12:43 -08:00
Cosmin Popescu
d60bab2082 gpio:c fix for gpio_group memory leak
Signed-off-by: Cosmin Popescu <gabrielcosmin.popescu@gmail.com>
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2019-03-06 12:12:34 -08:00
Cosmin Popescu
18b4ac5663 mraa.c: Fix memory leak
Signed-off-by: Cosmin Popescu <gabrielcosmin.popescu@gmail.com>
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2019-03-06 12:12:25 -08:00
Adelin Dobre
4ec830fcc6 jsonplatform.c: Add fix for passing null as parameter
Signed-off-by: Adelin Dobre <adelin.dobre@rinftech.com>
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2019-03-06 12:12:17 -08:00
Adelin Dobre
6e85bcd902 jsonplatform.c: Add fix for dereferencing of a null pointer
Signed-off-by: Adelin Dobre <adelin.dobre@rinftech.com>
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2019-03-06 12:12:08 -08:00
Adelin Dobre
1278089e84 initio.c: Add fix for potential leak memory
Signed-off-by: Adelin Dobre <adelin.dobre@rinftech.com>
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2019-03-06 12:11:50 -08:00
Adelin Dobre
ba201fcad2 initio.c: Add fix for passing null as parameter
Signed-off-by: Adelin Dobre <adelin.dobre@rinftech.com>
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2019-03-06 12:11:42 -08:00
Adelin Dobre
8ded6f1f6d initio.c: Add fix for passing null pointer as argument
Signed-off-by: Adelin Dobre <adelin.dobre@rinftech.com>
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2019-03-06 12:11:33 -08:00
Cosmin Popescu
88a8bb22b6 mraa.c: Add fix for dereferencing of a null pointer
Signed-off-by: Cosmin Popescu <gabrielcosmin.popescu@gmail.com>
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2019-03-06 12:11:21 -08:00
Cosmin Popescu
9fe2883e6a gpio.c: Add fix for dereferencing of a null pointer
Signed-off-by: Cosmin Popescu <gabrielcosmin.popescu@gmail.com>
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2019-03-06 12:11:10 -08:00
Cosmin Popescu
5169021afd mraa.c: Add fix for potential memory leak
Signed-off-by: Cosmin Popescu <gabrielcosmin.popescu@gmail.com>
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2019-03-06 12:10:59 -08:00
Cosmin Popescu
6252d25729 x86/intel_galileo_rev_g.c: Removed switch break after return
Signed-off-by: Cosmin Popescu <gabrielcosmin.popescu@gmail.com>
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2019-03-06 12:10:48 -08:00
Cosmin Popescu
b75731d9d3 iio/iio.c: Fix typo
Signed-off-by: Cosmin Popescu <gabrielcosmin.popescu@gmail.com>
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2019-03-06 12:10:35 -08:00
Cosmin Popescu
9cb508f5d2 iio/iio.c: Add fix for access of variable before error check
Signed-off-by: Cosmin Popescu <gabrielcosmin.popescu@gmail.com>
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2019-03-06 12:10:06 -08:00
Cosmin Popescu
2bb200aa04 iio/iio.c: Add fix for division by 0 bug
Signed-off-by: Cosmin Popescu <gabrielcosmin.popescu@gmail.com>
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2019-03-06 12:09:51 -08:00
Sai Hari Chandana Kalluri
b425c99030 [PATCH] Ultra96: Add support for ultra96
Add support for Ultra96 board: Ultra96 is an Arm-based, Xilinx Zynq
UltraScale+ MPSoC development board based on the Linaro 96Boards
Consumer Edition specification.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Peter Ryser <peter.ryser@xilinx.com>
Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com>
Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
2019-02-23 20:46:49 +01:00
Burak Han
08b2cefebe DE10-Nano: Detection For Different Kernels
To detect DE10-Nano with default config.

Signed-off-by: Burak Han Corak<burakhancorak@gmail.com>
Signed-off-by: Thomas Ingleby <thomas.ingleby@intel.com>
2019-02-21 10:10:35 -08:00
Adelin Dobre
d0c884e67d initio.c: Fix parse issue inside mraa_io_init
Signed-off-by: Adelin Dobre <adelin.dobre@rinftech.com>
Signed-off-by: Thomas Ingleby <thomas.ingleby@intel.com>
2019-02-21 09:53:54 -08:00
Chuck Duey
eae4a0cfbf BeagleBone Fix detection of emmc and PCM for mraa pins 74-77
This fixes the problem of detecting if pins 74-77 are available for gpio/spi use.  These pins were sown to be used by the emmc, but actually used by the sound pcm.  If the sound PCM is disabled and the emmc is enabled the pinse can now be used.  mraa-gpio list output Pins 74-77
73     GPIO115: GPIO
74     GPIO113: GPIO SPI
75     GPIO111: GPIO SPI
76     GPIO112: GPIO SPI
77     GPIO110: GPIO SPI

to build:
1. clone repo
2. sudo apt-get install build-essential python-dev cmake automake libpcre3 libpcre3-dev byacc flex swig3.0
3. cd mraa, mkdir build, cd build
4. cmake -D CMAKE_INSTALL_PREFIX=/usr ..
5. make
6. sudo make install

This has been verified to work on BBGW, and BBBW with 9.0-9.5 with emmc enabled and PCM aduio turned off.  It is so nice to have control of these pins when running with out an SD card.

Closes #953

Signed-off-by: Chuck Duey <cduey@msn.com>
Signed-off-by: Thomas Ingleby <thomas.ingleby@intel.com>
2019-02-21 09:50:11 -08:00
Brett Haines
7a1db249fe rpi: Added Raspberry Pi 3 A+ definitions
Signed-off-by: Brett Haines <bhaines418@gmail.com>
Signed-off-by: Thomas Ingleby <thomas.ingleby@intel.com>
2018-11-29 09:53:11 -08:00
Chuck Duey
d3207769e7 rpi: Added Raspberry Pi 3 B+ to Hardware Versions with corrections
Signed-off-by: Chuck Duey <cduey@msn.com>
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2018-10-09 09:58:36 -07:00
Manivannan Sadhasivam
b07633c38a 96boards: Add onboard LED support for Dragonboard410c
Add onboard LED support for Dragonboard410c. There are 4 user LEDs and
two LEDs for BT and WLAN.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-09-05 09:05:26 +05:30
Manivannan Sadhasivam
6fcd882d58 led: Add support for initializing onboard LEDs based on board definition
1. Add support for initializing onboard LEDs based on board definition.
Maximum LED count has been set to 12.

2. Introduce mraa_led_init_raw API for initializing LEDs based on
function name. This API can be used by platforms which doesn't have mapping
in board definition.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-09-05 09:05:26 +05:30
Manivannan Sadhasivam
6c0ec10ba1 96boards: Configure SPI0_CS pin as GPIO for Dragonboard410c
On Dragonboard410c, configure SPI0_CS pin as GPIO for enabling the
user to control it without adding chip select property in Devicetree.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-08-30 22:23:15 +05:30
Manivannan Sadhasivam
77d4676616 mraa: fix mraa_gpio_lookup function
1. Extend the lookup count to phy_pin_count to cover all physical pins
   exposed on the board
2. Ignore the non GPIO pins by checking for GPIO capability

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-08-15 08:53:04 +05:30
Manivannan Sadhasivam
9056556b7a 96boards: Add Ultra-96 board support
This commit adds Ultra96, one of the Consumer Edition boards of the
96Boards family.

Ultra96 is an Arm-based, Xilinx Zynq UltraScale+ MPSoC development board.
This board runs petalinux distribution on the ARM core and integrates
Xilinx programmable logic (PL) UltraScale architecture in a single fabric.

This board supports standard peripherals defined by 96Boards CE
Specification. Since it ships with >4.8 kernel, only chardev mapping
is supported for accessing GPIO.

More information about this board can be found in 96Boards product
page: https://www.96boards.org/product/ultra96/

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2018-07-29 23:13:30 +05:30