d954599045
UP Xtreme is based on the Intel(R) Core(TM) i3/i5/i7 Whiskey Lake SoCs. The UP Xtreme presents one Raspberry Pi compatible HAT connector. This implementaion supports i2c, spi, uart, adc and gpio through the 40pin HAT connector. Gpio chardev capabilities have been disabled in this implementation. When gpio chardev capabilities are enabled an input becomes unreadable after an isr has been registered to the pin. See here for details: https://github.com/intel-iot-devkit/mraa/issues/937 Tested on UP Xtreme, with UP Board Linux kernel 5.0.0 Features tested: gpio, gpio interrupts, i2c, spi, adc and uart. Signed-off-by: Michael Campion <michael.campion@emutex.com>
272 lines
11 KiB
C
272 lines
11 KiB
C
/*
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* Author: Brendan Le Foll <brendan.le.foll@intel.com>
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* SPDX-License-Identifier: MIT
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*/
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#pragma once
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/** @file
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*
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* This file defines the basic shared types for libmraa
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* this file is different to common.h in that swig takes this as an input
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* MRAA supported platform types
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*/
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typedef enum {
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MRAA_INTEL_GALILEO_GEN1 = 0, /**< The Generation 1 Galileo platform (RevD) */
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MRAA_INTEL_GALILEO_GEN2 = 1, /**< The Generation 2 Galileo platform (RevG/H) */
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MRAA_INTEL_EDISON_FAB_C = 2, /**< The Intel Edison (FAB C) */
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MRAA_INTEL_DE3815 = 3, /**< The Intel DE3815 Baytrail NUC */
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MRAA_INTEL_MINNOWBOARD_MAX = 4, /**< The Intel Minnow Board Max */
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MRAA_RASPBERRY_PI = 5, /**< The different Raspberry PI Models -like A,B,A+,B+ */
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MRAA_BEAGLEBONE = 6, /**< The different BeagleBone Black Modes B/C */
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MRAA_BANANA = 7, /**< Allwinner A20 based Banana Pi and Banana Pro */
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MRAA_INTEL_NUC5 = 8, /**< The Intel 5th generations Broadwell NUCs */
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MRAA_96BOARDS = 9, /**< Linaro 96boards */
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MRAA_INTEL_SOFIA_3GR = 10, /**< The Intel SoFIA 3GR */
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MRAA_INTEL_CHERRYHILLS = 11, /**< The Intel Braswell Cherryhills */
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MRAA_UP = 12, /**< The UP Board */
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MRAA_INTEL_JOULE_EXPANSION = 13,/**< The Intel Joule Expansion Board */
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#if __STDC_VERSION__ >= 199901L
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MRAA_INTEL_GT_TUCHUCK = MRAA_INTEL_JOULE_EXPANSION, // deprecated
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#endif
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MRAA_PHYBOARD_WEGA = 14, /**< The phyBOARD-Wega */
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MRAA_DE_NANO_SOC = 15, /**< Terasic DE-Nano-SoC Board */
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MRAA_UP2 = 16, /**< The UP^2 Board */
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MRAA_MTK_LINKIT = 17, /**< Mediatek MT7688 based Linkit boards */
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MRAA_MTK_OMEGA2 = 18, /**< MT7688 based Onion Omega2 board */
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MRAA_IEI_TANK = 19, /**< IEI Tank System*/
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MRAA_ROCKPI4 = 20, /**< Radxa ROCK PI 4 Models A/B */
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MRAA_ADLINK_IPI = 21, /**< Adlink Industrial PI */
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MRAA_ADLINK_LEC_AL = 22, /**< Adlink LEC-AL*/
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MRAA_ADLINK_LEC_AL_AI = 23, /**< Adlink LEC-AL*/
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MRAA_UPXTREME = 24, /**< The UPXTREME Board */
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// USB platform extenders start at 256
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MRAA_FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */
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// contains bit 9 so is subplatform
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MRAA_GROVEPI = 1024, /**< GrovePi shield i2c bridge */
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MRAA_GENERIC_FIRMATA = 1280, /**< Firmata uart platform/bridge */
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MRAA_ANDROID_PERIPHERALMANAGER = 95, /**< Android Things peripheral manager platform */
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MRAA_MOCK_PLATFORM = 96, /**< Mock platform, which requires no real hardware */
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MRAA_JSON_PLATFORM = 97, /**< User initialised platform from json */
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MRAA_NULL_PLATFORM = 98, /**< Platform with no capabilities that hosts a sub platform */
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MRAA_UNKNOWN_PLATFORM = 99 /**< An unknown platform type, typically will load INTEL_GALILEO_GEN1 */
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} mraa_platform_t;
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/**
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* Intel edison miniboard numbering enum
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*/
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typedef enum {
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MRAA_INTEL_EDISON_MINIBOARD_J17_1 = 0,
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MRAA_INTEL_EDISON_MINIBOARD_J17_5 = 4,
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MRAA_INTEL_EDISON_MINIBOARD_J17_7 = 6,
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MRAA_INTEL_EDISON_MINIBOARD_J17_8 = 7,
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MRAA_INTEL_EDISON_MINIBOARD_J17_9 = 8,
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MRAA_INTEL_EDISON_MINIBOARD_J17_10 = 9,
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MRAA_INTEL_EDISON_MINIBOARD_J17_11 = 10,
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MRAA_INTEL_EDISON_MINIBOARD_J17_12 = 11,
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MRAA_INTEL_EDISON_MINIBOARD_J17_14 = 13,
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MRAA_INTEL_EDISON_MINIBOARD_J18_1 = 14,
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MRAA_INTEL_EDISON_MINIBOARD_J18_2 = 15,
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MRAA_INTEL_EDISON_MINIBOARD_J18_6 = 19,
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MRAA_INTEL_EDISON_MINIBOARD_J18_7 = 20,
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MRAA_INTEL_EDISON_MINIBOARD_J18_8 = 21,
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MRAA_INTEL_EDISON_MINIBOARD_J18_10 = 23,
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MRAA_INTEL_EDISON_MINIBOARD_J18_11 = 24,
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MRAA_INTEL_EDISON_MINIBOARD_J18_12 = 25,
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MRAA_INTEL_EDISON_MINIBOARD_J18_13 = 26,
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MRAA_INTEL_EDISON_MINIBOARD_J19_4 = 31,
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MRAA_INTEL_EDISON_MINIBOARD_J19_5 = 32,
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MRAA_INTEL_EDISON_MINIBOARD_J19_6 = 33,
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MRAA_INTEL_EDISON_MINIBOARD_J19_8 = 35,
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MRAA_INTEL_EDISON_MINIBOARD_J19_9 = 36,
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MRAA_INTEL_EDISON_MINIBOARD_J19_10 = 37,
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MRAA_INTEL_EDISON_MINIBOARD_J19_11 = 38,
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MRAA_INTEL_EDISON_MINIBOARD_J19_12 = 39,
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MRAA_INTEL_EDISON_MINIBOARD_J19_13 = 40,
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MRAA_INTEL_EDISON_MINIBOARD_J19_14 = 41,
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MRAA_INTEL_EDISON_MINIBOARD_J20_3 = 44,
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MRAA_INTEL_EDISON_MINIBOARD_J20_4 = 45,
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MRAA_INTEL_EDISON_MINIBOARD_J20_5 = 46,
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MRAA_INTEL_EDISON_MINIBOARD_J20_6 = 47,
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MRAA_INTEL_EDISON_MINIBOARD_J20_7 = 48,
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MRAA_INTEL_EDISON_MINIBOARD_J20_8 = 49,
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MRAA_INTEL_EDISON_MINIBOARD_J20_9 = 50,
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MRAA_INTEL_EDISON_MINIBOARD_J20_10 = 51,
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MRAA_INTEL_EDISON_MINIBOARD_J20_11 = 52,
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MRAA_INTEL_EDISON_MINIBOARD_J20_12 = 53,
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MRAA_INTEL_EDISON_MINIBOARD_J20_13 = 54,
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MRAA_INTEL_EDISON_MINIBOARD_J20_14 = 55
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} mraa_intel_edison_miniboard_t;
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/**
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* Intel Edison raw GPIO numbering enum
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*/
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typedef enum {
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MRAA_INTEL_EDISON_GP182 = 0,
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MRAA_INTEL_EDISON_GP135 = 4,
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MRAA_INTEL_EDISON_GP27 = 6,
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MRAA_INTEL_EDISON_GP20 = 7,
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MRAA_INTEL_EDISON_GP28 = 8,
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MRAA_INTEL_EDISON_GP111 = 0,
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MRAA_INTEL_EDISON_GP109 = 10,
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MRAA_INTEL_EDISON_GP115 = 11,
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MRAA_INTEL_EDISON_GP128 = 13,
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MRAA_INTEL_EDISON_GP13 = 14,
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MRAA_INTEL_EDISON_GP165 = 15,
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MRAA_INTEL_EDISON_GP19 = 19,
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MRAA_INTEL_EDISON_GP12 = 20,
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MRAA_INTEL_EDISON_GP183 = 21,
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MRAA_INTEL_EDISON_GP110 = 23,
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MRAA_INTEL_EDISON_GP114 = 24,
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MRAA_INTEL_EDISON_GP129 = 25,
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MRAA_INTEL_EDISON_GP130 = 26,
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MRAA_INTEL_EDISON_GP44 = 31,
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MRAA_INTEL_EDISON_GP46 = 32,
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MRAA_INTEL_EDISON_GP48 = 33,
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MRAA_INTEL_EDISON_GP131 = 35,
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MRAA_INTEL_EDISON_GP14 = 36,
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MRAA_INTEL_EDISON_GP40 = 37,
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MRAA_INTEL_EDISON_GP43 = 38,
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MRAA_INTEL_EDISON_GP77 = 39,
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MRAA_INTEL_EDISON_GP82 = 40,
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MRAA_INTEL_EDISON_GP83 = 41,
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MRAA_INTEL_EDISON_GP134 = 44,
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MRAA_INTEL_EDISON_GP45 = 45,
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MRAA_INTEL_EDISON_GP47 = 46,
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MRAA_INTEL_EDISON_GP49 = 47,
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MRAA_INTEL_EDISON_GP15 = 48,
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MRAA_INTEL_EDISON_GP84 = 49,
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MRAA_INTEL_EDISON_GP42 = 50,
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MRAA_INTEL_EDISON_GP41 = 51,
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MRAA_INTEL_EDISON_GP78 = 52,
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MRAA_INTEL_EDISON_GP79 = 53,
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MRAA_INTEL_EDISON_GP80 = 54,
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MRAA_INTEL_EDISON_GP81 = 55
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} mraa_intel_edison_t;
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/**
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* Raspberry PI Wiring compatible numbering enum
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*/
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typedef enum {
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MRAA_RASPBERRY_WIRING_PIN8 = 3,
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MRAA_RASPBERRY_WIRING_PIN9 = 5,
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MRAA_RASPBERRY_WIRING_PIN7 = 7,
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MRAA_RASPBERRY_WIRING_PIN15 = 8,
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MRAA_RASPBERRY_WIRING_PIN16 = 10,
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MRAA_RASPBERRY_WIRING_PIN0 = 11,
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MRAA_RASPBERRY_WIRING_PIN1 = 12,
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MRAA_RASPBERRY_WIRING_PIN2 = 13,
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MRAA_RASPBERRY_WIRING_PIN3 = 15,
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MRAA_RASPBERRY_WIRING_PIN4 = 16,
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MRAA_RASPBERRY_WIRING_PIN5 = 18,
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MRAA_RASPBERRY_WIRING_PIN12 = 19,
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MRAA_RASPBERRY_WIRING_PIN13 = 21,
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MRAA_RASPBERRY_WIRING_PIN6 = 22,
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MRAA_RASPBERRY_WIRING_PIN14 = 23,
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MRAA_RASPBERRY_WIRING_PIN10 = 24,
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MRAA_RASPBERRY_WIRING_PIN11 = 26,
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MRAA_RASPBERRY_WIRING_PIN17 = 29, // RPi B V2
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MRAA_RASPBERRY_WIRING_PIN21 = 29,
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MRAA_RASPBERRY_WIRING_PIN18 = 30, // RPi B V2
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MRAA_RASPBERRY_WIRING_PIN19 = 31, // RPI B V2
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MRAA_RASPBERRY_WIRING_PIN22 = 31,
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MRAA_RASPBERRY_WIRING_PIN20 = 32, // RPi B V2
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MRAA_RASPBERRY_WIRING_PIN26 = 32,
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MRAA_RASPBERRY_WIRING_PIN23 = 33,
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MRAA_RASPBERRY_WIRING_PIN24 = 35,
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MRAA_RASPBERRY_WIRING_PIN27 = 36,
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MRAA_RASPBERRY_WIRING_PIN25 = 37,
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MRAA_RASPBERRY_WIRING_PIN28 = 38,
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MRAA_RASPBERRY_WIRING_PIN29 = 40
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} mraa_raspberry_wiring_t;
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/**
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* MRAA return codes
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*/
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typedef enum {
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MRAA_SUCCESS = 0, /**< Expected response */
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MRAA_ERROR_FEATURE_NOT_IMPLEMENTED = 1, /**< Feature TODO */
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MRAA_ERROR_FEATURE_NOT_SUPPORTED = 2, /**< Feature not supported by HW */
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MRAA_ERROR_INVALID_VERBOSITY_LEVEL = 3, /**< Verbosity level wrong */
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MRAA_ERROR_INVALID_PARAMETER = 4, /**< Parameter invalid */
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MRAA_ERROR_INVALID_HANDLE = 5, /**< Handle invalid */
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MRAA_ERROR_NO_RESOURCES = 6, /**< No resource of that type avail */
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MRAA_ERROR_INVALID_RESOURCE = 7, /**< Resource invalid */
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MRAA_ERROR_INVALID_QUEUE_TYPE = 8, /**< Queue type incorrect */
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MRAA_ERROR_NO_DATA_AVAILABLE = 9, /**< No data available */
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MRAA_ERROR_INVALID_PLATFORM = 10, /**< Platform not recognised */
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MRAA_ERROR_PLATFORM_NOT_INITIALISED = 11, /**< Board information not initialised */
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MRAA_ERROR_UART_OW_SHORTED = 12, /**< UART OW Short Circuit Detected*/
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MRAA_ERROR_UART_OW_NO_DEVICES = 13, /**< UART OW No devices detected */
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MRAA_ERROR_UART_OW_DATA_ERROR = 14, /**< UART OW Data/Bus error detected */
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MRAA_ERROR_UNSPECIFIED = 99 /**< Unknown Error */
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} mraa_result_t;
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/**
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* Enum representing different possible modes for a pin.
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*/
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typedef enum {
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MRAA_PIN_VALID = 0, /**< Pin Valid */
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MRAA_PIN_GPIO = 1, /**< General Purpose IO */
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MRAA_PIN_PWM = 2, /**< Pulse Width Modulation */
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MRAA_PIN_FAST_GPIO = 3, /**< Faster GPIO */
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MRAA_PIN_SPI = 4, /**< SPI */
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MRAA_PIN_I2C = 5, /**< I2C */
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MRAA_PIN_AIO = 6, /**< Analog in */
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MRAA_PIN_UART = 7 /**< UART */
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} mraa_pinmodes_t;
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/**
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* Enum reprensenting different i2c speeds/modes
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*/
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typedef enum {
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MRAA_I2C_STD = 0, /**< up to 100Khz */
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MRAA_I2C_FAST = 1, /**< up to 400Khz */
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MRAA_I2C_HIGH = 2 /**< up to 3.4Mhz */
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} mraa_i2c_mode_t;
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/**
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* Enum representing different uart parity states
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*/
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typedef enum {
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MRAA_UART_PARITY_NONE = 0,
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MRAA_UART_PARITY_EVEN = 1,
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MRAA_UART_PARITY_ODD = 2,
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MRAA_UART_PARITY_MARK = 3,
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MRAA_UART_PARITY_SPACE = 4
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} mraa_uart_parity_t;
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#ifdef __cplusplus
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}
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#endif
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