Beaglebone AIO pins seem to be a little different than most boards, so
this is my attempt to work with that without impacting other boards. I
added a new flag in mraa_board_t to indicate whether or not the aio pins
are sequential. One the beaglebone, they are not. To go along with this,
I added a new device mraa_aio_dev_t, that will map each aio to a
physical pin.
In the main aio logic, if aio_non_seq is true for the board, the manual
mapping is used, otherwise the old mathematical mapping is used.
Signed-off-by: Nick Crast <nrcrast@gmail.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
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