styling: convert TAB to four SPACES
Signed-off-by: Kiveisha Yevgeniy <yevgeniy.kiveisha@intel.com>
This commit is contained in:
Kiveisha Yevgeniy
@@ -29,90 +29,90 @@
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#include <maa/spi.h>
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/* Memory Map */
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#define CONFIG 0x00
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#define EN_AA 0x01
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#define EN_RXADDR 0x02
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#define SETUP_AW 0x03
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#define SETUP_RETR 0x04
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#define RF_CH 0x05
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#define RF_SETUP 0x06
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#define STATUS 0x07
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#define OBSERVE_TX 0x08
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#define CD 0x09
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#define RX_ADDR_P0 0x0A
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#define RX_ADDR_P1 0x0B
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#define RX_ADDR_P2 0x0C
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#define RX_ADDR_P3 0x0D
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#define RX_ADDR_P4 0x0E
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#define RX_ADDR_P5 0x0F
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#define TX_ADDR 0x10
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#define RX_PW_P0 0x11
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#define RX_PW_P1 0x12
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#define RX_PW_P2 0x13
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#define RX_PW_P3 0x14
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#define RX_PW_P4 0x15
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#define RX_PW_P5 0x16
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#define FIFO_STATUS 0x17
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#define CONFIG 0x00
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#define EN_AA 0x01
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#define EN_RXADDR 0x02
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#define SETUP_AW 0x03
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#define SETUP_RETR 0x04
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#define RF_CH 0x05
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#define RF_SETUP 0x06
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#define STATUS 0x07
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#define OBSERVE_TX 0x08
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#define CD 0x09
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#define RX_ADDR_P0 0x0A
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#define RX_ADDR_P1 0x0B
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#define RX_ADDR_P2 0x0C
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#define RX_ADDR_P3 0x0D
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#define RX_ADDR_P4 0x0E
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#define RX_ADDR_P5 0x0F
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#define TX_ADDR 0x10
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#define RX_PW_P0 0x11
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#define RX_PW_P1 0x12
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#define RX_PW_P2 0x13
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#define RX_PW_P3 0x14
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#define RX_PW_P4 0x15
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#define RX_PW_P5 0x16
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#define FIFO_STATUS 0x17
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/* Bit Mnemonics */
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#define MASK_RX_DR 6
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#define MASK_TX_DS 5
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#define MASK_MAX_RT 4
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#define EN_CRC 3
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#define CRCO 2
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#define PWR_UP 1
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#define PRIM_RX 0
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#define ENAA_P5 5
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#define ENAA_P4 4
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#define ENAA_P3 3
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#define ENAA_P2 2
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#define ENAA_P1 1
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#define ENAA_P0 0
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#define ERX_P5 5
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#define ERX_P4 4
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#define ERX_P3 3
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#define ERX_P2 2
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#define ERX_P1 1
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#define ERX_P0 0
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#define AW 0
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#define ARD 4
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#define ARC 0
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#define PLL_LOCK 4
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#define RF_DR 3
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#define RF_PWR 1
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#define LNA_HCURR 0
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#define RX_DR 6
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#define TX_DS 5
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#define MAX_RT 4
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#define RX_P_NO 1
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#define TX_FULL 0
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#define PLOS_CNT 4
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#define ARC_CNT 0
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#define TX_REUSE 6
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#define FIFO_FULL 5
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#define TX_EMPTY 4
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#define RX_FULL 1
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#define RX_EMPTY 0
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#define MASK_RX_DR 6
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#define MASK_TX_DS 5
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#define MASK_MAX_RT 4
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#define EN_CRC 3
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#define CRCO 2
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#define PWR_UP 1
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#define PRIM_RX 0
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#define ENAA_P5 5
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#define ENAA_P4 4
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#define ENAA_P3 3
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#define ENAA_P2 2
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#define ENAA_P1 1
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#define ENAA_P0 0
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#define ERX_P5 5
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#define ERX_P4 4
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#define ERX_P3 3
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#define ERX_P2 2
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#define ERX_P1 1
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#define ERX_P0 0
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#define AW 0
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#define ARD 4
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#define ARC 0
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#define PLL_LOCK 4
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#define RF_DR 3
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#define RF_PWR 1
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#define LNA_HCURR 0
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#define RX_DR 6
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#define TX_DS 5
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#define MAX_RT 4
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#define RX_P_NO 1
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#define TX_FULL 0
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#define PLOS_CNT 4
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#define ARC_CNT 0
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#define TX_REUSE 6
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#define FIFO_FULL 5
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#define TX_EMPTY 4
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#define RX_FULL 1
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#define RX_EMPTY 0
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/* Instruction Mnemonics */
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#define R_REGISTER 0x00
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#define W_REGISTER 0x20
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#define REGISTER_MASK 0x1F
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#define R_RX_PAYLOAD 0x61
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#define W_TX_PAYLOAD 0xA0
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#define FLUSH_TX 0xE1
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#define FLUSH_RX 0xE2
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#define REUSE_TX_PL 0xE3
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#define NOP 0xFF
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#define R_REGISTER 0x00
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#define W_REGISTER 0x20
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#define REGISTER_MASK 0x1F
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#define R_RX_PAYLOAD 0x61
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#define W_TX_PAYLOAD 0xA0
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#define FLUSH_TX 0xE1
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#define FLUSH_RX 0xE2
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#define REUSE_TX_PL 0xE3
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#define NOP 0xFF
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/* Nrf24l settings */
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#define mirf_ADDR_LEN 5
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#define mirf_CONFIG ((1<<EN_CRC) | (0<<CRCO) )
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#define mirf_ADDR_LEN 5
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#define mirf_CONFIG ((1<<EN_CRC) | (0<<CRCO) )
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#define MAX_BUFFER 32
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#define MAX_BUFFER 32
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#define HIGH 1
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#define LOW 0
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#define HIGH 1
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#define LOW 0
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namespace upm {
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@@ -120,61 +120,61 @@ typedef void (* funcPtrVoidVoid) ();
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class NRF24l01 {
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public:
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NRF24l01 (uint8_t cs);
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~NRF24l01 ();
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std::string name()
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NRF24l01 (uint8_t cs);
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~NRF24l01 ();
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std::string name()
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{
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return m_name;
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}
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void nrfInitModule (uint8_t chipSelect, uint8_t chipEnable);
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void nrfConfigModule ();
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void nrfSend (uint8_t *value);
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void nrfSend ();
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void nrfSetRXaddr (uint8_t * addr);
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void nrfSetTXaddr (uint8_t * addr);
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void nrfSetBroadcastAddr (uint8_t * addr);
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void nrfSetPayload (uint8_t load);
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bool nrfDataReady ();
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bool nrfIsSending ();
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bool nrfRXFifoEmpty ();
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bool nrfTXFifoEmpty ();
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void nrfGetData (uint8_t * data);
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uint8_t nrfGetStatus ();
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void nrfTransmitSync (uint8_t *dataout, uint8_t len);
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void nrfTransferSync (uint8_t *dataout ,uint8_t *datain, uint8_t len);
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void nrfConfigRegister (uint8_t reg, uint8_t value);
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void nrfReadRegister (uint8_t reg, uint8_t * value, uint8_t len);
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void nrfWriteRegister (uint8_t reg, uint8_t * value, uint8_t len);
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void nrfPowerUpRX ();
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void nrfPowerUpTX ();
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void nrfPowerDown ();
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void nrfInitModule (uint8_t chipSelect, uint8_t chipEnable);
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void nrfConfigModule ();
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void nrfSend (uint8_t *value);
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void nrfSend ();
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void nrfSetRXaddr (uint8_t * addr);
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void nrfSetTXaddr (uint8_t * addr);
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void nrfSetBroadcastAddr (uint8_t * addr);
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void nrfSetPayload (uint8_t load);
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bool nrfDataReady ();
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bool nrfIsSending ();
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bool nrfRXFifoEmpty ();
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bool nrfTXFifoEmpty ();
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void nrfGetData (uint8_t * data);
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uint8_t nrfGetStatus ();
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void nrfTransmitSync (uint8_t *dataout, uint8_t len);
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void nrfTransferSync (uint8_t *dataout ,uint8_t *datain, uint8_t len);
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void nrfConfigRegister (uint8_t reg, uint8_t value);
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void nrfReadRegister (uint8_t reg, uint8_t * value, uint8_t len);
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void nrfWriteRegister (uint8_t reg, uint8_t * value, uint8_t len);
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void nrfPowerUpRX ();
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void nrfPowerUpTX ();
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void nrfPowerDown ();
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maa_result_t nrfCEHigh ();
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maa_result_t nrfCELow ();
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maa_result_t nrfCSOn ();
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maa_result_t nrfCSOff ();
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void nrfFlushRX ();
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void nrfListenForChannel();
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maa_result_t nrfCEHigh ();
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maa_result_t nrfCELow ();
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maa_result_t nrfCSOn ();
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maa_result_t nrfCSOff ();
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void nrfFlushRX ();
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void nrfListenForChannel();
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uint8_t m_rxBuffer[MAX_BUFFER];
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uint8_t m_txBuffer[MAX_BUFFER];
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uint8_t m_rxBuffer[MAX_BUFFER];
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uint8_t m_txBuffer[MAX_BUFFER];
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funcPtrVoidVoid dataRecievedHandler;
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private:
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maa_spi_context m_spi;
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uint8_t m_ce;
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uint8_t m_csn;
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uint8_t m_channel;
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uint8_t m_ptx;
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uint8_t m_payload;
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uint8_t m_localAddress[5];
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maa_gpio_context m_csnPinCtx;
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maa_gpio_context m_cePinCtx;
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funcPtrVoidVoid dataRecievedHandler;
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private:
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maa_spi_context m_spi;
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uint8_t m_ce;
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uint8_t m_csn;
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uint8_t m_channel;
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uint8_t m_ptx;
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uint8_t m_payload;
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uint8_t m_localAddress[5];
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maa_gpio_context m_csnPinCtx;
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maa_gpio_context m_cePinCtx;
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std::string m_name;
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std::string m_name;
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};
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}
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