Since UPM Travis-CI runs ctests (one of which loads python examples), the added lines would fail if the RSC_DATA_RATE and RSC_MODE have not been included in the python rsc module.) Signed-off-by: Noel Eck <noel.eck@intel.com>
Since UPM Travis-CI runs ctests (one of which loads python examples), the added lines would fail if the RSC_DATA_RATE and RSC_MODE have not been included in the python rsc module.) Signed-off-by: Noel Eck <noel.eck@intel.com>