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de10-nano: added initial support for Terasic DE10-Nano-SoC kit

Browse Source 
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
This commit is contained in:
root
2017-02-20 15:49:48 -08:00
committed by Brendan Le Foll
parent 0470aebee6
commit 0004dfeefb
7 changed files with 609 additions and 0 deletions
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4
README.md
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@@ -38,6 +38,10 @@ ARM
* [Beaglebone Black](../master/docs/beaglebone.md)
* [phyBOARD-Wega](../master/docs/phyboard-wega.md)
FPGA
----
* [DE10-Nano](../master/docs/altera-socfpga.md)
USB
---
* [FT4222](../master/docs/ftdi_ft4222.md)

1
api/mraa/types.h
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@@ -55,6 +55,7 @@ typedef enum {
MRAA_INTEL_GT_TUCHUCK = MRAA_INTEL_JOULE_EXPANSION, // deprecated
#endif
MRAA_PHYBOARD_WEGA = 14, /**< The phyBOARD-Wega */
MRAA_ALTERA_SOCFPGA = 15, /** < Terasic DE-Nano-SoC Board */
// USB platform extenders start at 256
MRAA_FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */

145
docs/altera-socfpga.md Normal file
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@@ -0,0 +1,145 @@
Terasic DE10-Nano {#de10-nano}
=================
The DE10-Nano Development Kit presents a robust hardware design platform built around the Intel
System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with
industry-leading programmable logic for ultimate design flexibility. Users can now leverage the
power of tremendous re-configurability paired with a high-performance, low-power processor system.
Altera’s SoC integrates an ARM-based hard processor system (HPS) consisting of processor,
peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth
interconnect backbone. The DE10-Nano development board is equipped with high-speed DDR3 memory,
analog to digital capabilities, Ethernet networking, and much more that promise many exciting
applications.
Board Support
-------------
Terasic DE10-Nano
Terasic DE0-Nano-SoC
Protocol Notes
---------------
**GPIO** Fully supported through sysfs (both FPGA + HPC). Mmap not yet supported. Static map.
**PWM** Currently not supported.
**I2C** Fully supported with i2cdev. Default bus 2 is exposed on Arduino header, 3 buses total.
**SPI** Supported with spidev on Arduino header.
**UART** Working, default bus is on Arduino header. Console also accessible as `ttyS0` in raw mode.
**ADC** Currently not supported.
No muxes available for multi-function pins yet (e.g. you won't be able to use D0 & D1 on Arduino
header as GPIOs).
Pin Mapping
-----------
**Arduino Header**
| MRAA Number | Arduino Name | Board Pin | Function |
|-------------|--------------|-----------|----------|
| 0 | D0 | JP3-8 | UART RX |
| 1 | D1 | JP3-7 | UART TX |
| 2 | D2 | JP3-6 | GPIO |
| 3 | D3 | JP3-5 | GPIO |
| 4 | D4 | JP3-4 | GPIO |
| 5 | D5 | JP3-3 | GPIO |
| 6 | D6 | JP3-2 | GPIO |
| 7 | D7 | JP3-1 | GPIO |
| 8 | D8 | JP2-10 | GPIO |
| 9 | D9 | JP2-9 | GPIO |
| 10 | D10 | JP2-8 | SPI SS |
| 11 | D11 | JP2-7 | SPI MOSI |
| 12 | D12 | JP2-6 | SPI MISO |
| 13 | D13 | JP2-5 | SPI SCK |
| 14 | GND | JP2-4 | - |
| 15 | AREF | JP2-3 | - |
| 16 | SDA | JP2-2 | I2C SDA |
| 17 | SCL | JP2-1 | I2C SCL |
| 18 | AREF | JP5-1 | - |
| 19 | IOREF | JP5-2 | - |
| 20 | RESET | JP5-3 | - |
| 21 | 3V3 | JP5-4 | - |
| 22 | 5V | JP5-5 | - |
| 23 | GND | JP5-6 | - |
| 24 | GND | JP5-7 | - |
| 25 | VIN | JP5-8 | - |
| 26 | A0 | JP6-1 | AIO |
| 27 | A1 | JP6-2 | AIO |
| 28 | A2 | JP6-3 | AIO |
| 29 | A3 | JP6-4 | AIO |
| 30 | A4 | JP6-5 | AIO |
| 31 | A5 | JP6-6 | AIO |
** GPIO0 (JP1) Side Header **
| MRAA Number | Board Pin | Function |
|-------------|-----------|----------|
| 32 | JP1-1 | GPIO |
| ... | ... | GPIO |
| 41 | JP1-10 | GPIO |
| 42 | JP1-11 | 5V |
| 43 | JP1-12 | GND |
| 44 | JP1-13 | GPIO |
| ... | ... | GPIO |
| 59 | JP1-28 | GPIO |
| 60 | JP1-29 | 3V3 |
| 61 | JP1-30 | GND |
| 62 | JP1-31 | GPIO |
| ... | ... | GPIO |
| 71 | JP1-40 | GPIO |
** GPIO1 (JP7) Side Header **
| MRAA Number | Board Pin | Function |
|-------------|-----------|----------|
| 72 | JP7-1 | GPIO |
| ... | ... | GPIO |
| 81 | JP7-10 | GPIO |
| 82 | JP7-11 | 5V |
| 83 | JP7-12 | GND |
| 84 | JP7-13 | GPIO |
| ... | ... | GPIO |
| 99 | JP7-28 | GPIO |
| 100 | JP7-29 | 3V3 |
| 101 | JP7-30 | GND |
| 102 | JP7-31 | GPIO |
| ... | ... | GPIO |
| 111 | JP7-40 | GPIO |
** Switches, Buttons, LEDs **
These are already in use by kernel drivers with the default image, except for KEY0 and KEY1.
To use them with MRAA remove them from the device tree.
To enable the switches temporarily (until reboot):
```sh
echo ff204000.gpio >/sys/bus/platform/drivers/altera_gpio/unbind
echo ff204000.gpio >/sys/bus/platform/drivers/altera_gpio/bind
```
And for LEDs:
```sh
echo ff203000.gpio >/sys/bus/platform/drivers/altera_gpio/unbind
echo ff203000.gpio >/sys/bus/platform/drivers/altera_gpio/bind
```
| MRAA Number | Board Pin | Function |
|-------------|-----------|----------|
| 112 | SW0 | GPIO |
| 113 | SW1 | GPIO |
| 114 | SW2 | GPIO |
| 115 | SW3 | GPIO |
| 116 | LED0 | GPIO |
| 117 | LED1 | GPIO |
| 118 | LED2 | GPIO |
| 119 | LED3 | GPIO |
| 120 | LED4 | GPIO |
| 121 | LED5 | GPIO |
| 122 | LED6 | GPIO |
| 123 | LED7 | GPIO |
| 124 | HPS_LED | GPIO |
| 125 | HPS_KEY | GPIO |
| 126 | KEY0 | GPIO |
| 127 | KEY1 | GPIO |

43
include/arm/altera_socfpga.h Normal file
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@@ -0,0 +1,43 @@
/*
* Author: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
* Copyright (c) 2017 Intel Corporation.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "mraa_internal.h"
// 1x32 Arduino header, 1x40 GPIO_0/JP1, 1x40 GPIO_1/JP7,
// 9 LEDs (8 User + HPS_LED), 4 switches, 3 buttons (2 User + HPS_KEY)
// 10 ADC pins
#define MRAA_ALTERA_SOCFPGA_PINCOUNT 138
mraa_board_t *
mraa_altera_socfpga();
#ifdef __cplusplus
}
#endif

1
src/CMakeLists.txt
View File

@@ -83,6 +83,7 @@ set (mraa_LIB_ARM_SRCS_NOAUTO
${PROJECT_SOURCE_DIR}/src/arm/beaglebone.c
${PROJECT_SOURCE_DIR}/src/arm/phyboard.c
${PROJECT_SOURCE_DIR}/src/arm/banana.c
${PROJECT_SOURCE_DIR}/src/arm/altera_socfpga.c
)
set (mraa_LIB_MOCK_SRCS_NOAUTO

409
src/arm/altera_socfpga.c Normal file
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@@ -0,0 +1,409 @@
/*
* Author: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
* Copyright (c) 2017 Intel Corporation.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <stdlib.h>
#include <string.h>
#include <sys/mman.h>
#include <mraa/common.h>
#include "common.h"
#include "arm/altera_socfpga.h"
#define PLATFORM_NAME "DE10-Nano-SoC"
#define SYSFS_CLASS_GPIO "/sys/class/gpio"
#define DEBUGFS_PINMODE_PATH "/sys/kernel/debug/gpio"
#define FPGA_REGION_BASE 0xFF200000
#define FPGA_REGION_SIZE 0x00200000
#define MMAP_PATH "/dev/mem"
// MMAP
static uint8_t* mmap_reg = NULL;
static int mmap_fd = 0;
static int mmap_size = FPGA_REGION_SIZE;
static unsigned int mmap_count = 0;
// MMAP stubbed functions
mraa_result_t
mraa_altera_socfpga_spi_init_pre(int index)
{
return MRAA_SUCCESS;
}
mraa_result_t
mraa_altera_socfpga_i2c_init_pre(unsigned int bus)
{
return MRAA_SUCCESS;
}
mraa_result_t
mraa_altera_socfpga_mmap_write(mraa_gpio_context dev, int value)
{
return MRAA_SUCCESS;
}
static mraa_result_t
mraa_altera_socfpga_mmap_unsetup()
{
if (mmap_reg == NULL) {
syslog(LOG_ERR, "altera_socfpga mmap: null register cant unsetup");
return MRAA_ERROR_INVALID_RESOURCE;
}
munmap(mmap_reg, mmap_size);
mmap_reg = NULL;
if (close(mmap_fd) != 0) {
return MRAA_ERROR_INVALID_RESOURCE;
}
return MRAA_SUCCESS;
}
int
mraa_altera_socfpga_mmap_read(mraa_gpio_context dev)
{
return 0;
}
mraa_result_t
mraa_altera_socfpga_mmap_setup(mraa_gpio_context dev, mraa_boolean_t en)
{
if (dev == NULL) {
syslog(LOG_ERR, "altera_socfpga mmap: context not valid");
return MRAA_ERROR_INVALID_HANDLE;
}
if (en == 0) {
if (dev->mmap_write == NULL && dev->mmap_read == NULL) {
syslog(LOG_ERR, "altera_socfpga mmap: can't disable disabled mmap gpio");
return MRAA_ERROR_INVALID_PARAMETER;
}
dev->mmap_write = NULL;
dev->mmap_read = NULL;
mmap_count--;
if (mmap_count == 0) {
return mraa_altera_socfpga_mmap_unsetup();
}
return MRAA_SUCCESS;
}
if (dev->mmap_write != NULL && dev->mmap_read != NULL) {
syslog(LOG_ERR, "altera_socfpga mmap: can't enable enabled mmap gpio");
return MRAA_ERROR_INVALID_PARAMETER;
}
// Might need to make some elements of this thread safe.
// For example only allow one thread to enter the following block
// to prevent mmap'ing twice.
if (mmap_reg == NULL) {
if ((mmap_fd = open(MMAP_PATH, O_RDWR)) < 0) {
syslog(LOG_ERR, "altera_socfpga map: unable to open resource0 file");
return MRAA_ERROR_INVALID_HANDLE;
}
mmap_reg = (uint8_t*) mmap(NULL, mmap_size, PROT_READ | PROT_WRITE, MAP_FILE | MAP_SHARED, mmap_fd, FPGA_REGION_BASE);
if (mmap_reg == MAP_FAILED) {
syslog(LOG_ERR, "altera_socfpga mmap: failed to mmap");
mmap_reg = NULL;
close(mmap_fd);
return MRAA_ERROR_NO_RESOURCES;
}
}
dev->mmap_write = &mraa_altera_socfpga_mmap_write;
dev->mmap_read = &mraa_altera_socfpga_mmap_read;
mmap_count++;
return MRAA_SUCCESS;
}
mraa_board_t*
mraa_altera_socfpga()
{
mraa_board_t* b = (mraa_board_t*) calloc(1, sizeof(mraa_board_t));
if (b == NULL) {
return NULL;
}
b->platform_name = PLATFORM_NAME;
b->phy_pin_count = MRAA_ALTERA_SOCFPGA_PINCOUNT;
b->gpio_count = 96; // update as needed when adding ADC pins
b->aio_count = 8;
//b->pwm_default_period = 5000;
//b->pwm_max_period = 218453;
//b->pwm_min_period = 1;
b->pins = (mraa_pininfo_t*) calloc(b->phy_pin_count, sizeof(mraa_pininfo_t));
if (b->pins == NULL) {
free(b);
return NULL;
}
b->adv_func = (mraa_adv_func_t*) calloc(1, sizeof(mraa_adv_func_t));
if (b->adv_func == NULL) {
free(b->pins);
free(b);
return NULL;
}
int pos = 0;
strncpy(b->pins[pos].name, "D0/RX", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 1 };
//b->pins[pos].gpio.pinmap = 0;
//b->pins[pos].gpio.mux_total = 0;
pos++;
strncpy(b->pins[pos].name, "D1/TX", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 1 };
//b->pins[pos].gpio.pinmap = 0;
//b->pins[pos].gpio.mux_total = 0;
pos++;
strncpy(b->pins[pos].name, "D2", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
b->pins[pos].gpio.pinmap = 203;
b->pins[pos].gpio.mux_total = 0;
pos++;
strncpy(b->pins[pos].name, "D3", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
b->pins[pos].gpio.pinmap = 204;
b->pins[pos].gpio.mux_total = 0;
pos++;
strncpy(b->pins[pos].name, "D4", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
b->pins[pos].gpio.pinmap = 205;
b->pins[pos].gpio.mux_total = 0;
pos++;
strncpy(b->pins[pos].name, "D5", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
b->pins[pos].gpio.pinmap = 206;
b->pins[pos].gpio.mux_total = 0;
pos++;
strncpy(b->pins[pos].name, "D6", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
b->pins[pos].gpio.pinmap = 207;
b->pins[pos].gpio.mux_total = 0;
pos++;
strncpy(b->pins[pos].name, "D7", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
b->pins[pos].gpio.pinmap = 208;
b->pins[pos].gpio.mux_total = 0;
pos++;
strncpy(b->pins[pos].name, "D8", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
b->pins[pos].gpio.pinmap = 209;
b->pins[pos].gpio.mux_total = 0;
pos++;
strncpy(b->pins[pos].name, "D9", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
b->pins[pos].gpio.pinmap = 210;
b->pins[pos].gpio.mux_total = 0;
pos++;
// TODO: add rest of the Arduino header
while (pos < 32) {
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
pos++;
}
// FPGA GPIO-0/JP1
int jp = 1;
int os_index = 171;
while (pos < 52) {
if (jp == 11) {
strncpy(b->pins[pos].name, "5V", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
} else if (jp == 12) {
strncpy(b->pins[pos].name, "GND", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
} else {
snprintf(b->pins[pos].name, 8, "JP1-%d", jp);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
b->pins[pos].gpio.pinmap = os_index;
b->pins[pos].gpio.mux_total = 0;
os_index++;
}
pos++;
jp++;
}
os_index = 139;
while (pos < 72) {
if (jp == 29) {
strncpy(b->pins[pos].name, "3V3", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
} else if (jp == 30) {
strncpy(b->pins[pos].name, "GND", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
} else {
snprintf(b->pins[pos].name, 8, "JP1-%d", jp);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
b->pins[pos].gpio.pinmap = os_index;
b->pins[pos].gpio.mux_total = 0;
os_index++;
}
pos++;
jp++;
}
// FPGA GPIO-1/JP7
jp = 1;
os_index = 107;
while (pos < 92) {
if (jp == 11) {
strncpy(b->pins[pos].name, "5V", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
} else if (jp == 12) {
strncpy(b->pins[pos].name, "GND", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
} else {
snprintf(b->pins[pos].name, 8, "JP7-%d", jp);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
b->pins[pos].gpio.pinmap = os_index;
b->pins[pos].gpio.mux_total = 0;
os_index++;
}
pos++;
jp++;
}
os_index = 75;
while (pos < 112) {
if (jp == 29) {
strncpy(b->pins[pos].name, "3V3", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
} else if (jp == 30) {
strncpy(b->pins[pos].name, "GND", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 0, 0, 0, 0, 0, 0, 0 };
} else {
snprintf(b->pins[pos].name, 8, "JP7-%d", jp);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
b->pins[pos].gpio.pinmap = os_index;
b->pins[pos].gpio.mux_total = 0;
os_index++;
}
pos++;
jp++;
}
// 4 Switches
jp = 0;
os_index = 363;
while (pos < 116) {
snprintf(b->pins[pos].name, 8, "SW%d", jp);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
b->pins[pos].gpio.pinmap = os_index;
b->pins[pos].gpio.mux_total = 0;
pos++;
jp++;
os_index++;
}
// 8 LEDs
jp = 0;
os_index = 395;
while (pos < 124) {
snprintf(b->pins[pos].name, 8, "LED%d", jp);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
b->pins[pos].gpio.pinmap = os_index;
b->pins[pos].gpio.mux_total = 0;
pos++;
jp++;
os_index++;
}
// HPS_LED, HPS_KEY0, KEY0, KEY1
strncpy(b->pins[pos].name, "HPS_LED", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
b->pins[pos].gpio.pinmap = 478;
b->pins[pos].gpio.mux_total = 0;
pos++;
strncpy(b->pins[pos].name, "HPS_KEY", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
b->pins[pos].gpio.pinmap = 479;
b->pins[pos].gpio.mux_total = 0;
pos++;
strncpy(b->pins[pos].name, "KEY0", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
b->pins[pos].gpio.pinmap = 331;
b->pins[pos].gpio.mux_total = 0;
pos++;
strncpy(b->pins[pos].name, "KEY1", 8);
b->pins[pos].capabilities = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
b->pins[pos].gpio.pinmap = 332;
b->pins[pos].gpio.mux_total = 0;
pos++;
// Bus definitions
// No function muxing needed for buses (stubbed pins if added later)
b->no_bus_mux = 1;
// 3 I2C buses (default 2 from Arduino header)
b->i2c_bus_count = 3;
b->def_i2c_bus = 2;
b->i2c_bus[0].bus_id = 0;
//b->i2c_bus[0].sda = 0;
//b->i2c_bus[0].scl = 0;
b->i2c_bus[1].bus_id = 1;
//b->i2c_bus[1].sda = 0;
//b->i2c_bus[1].scl = 0;
b->i2c_bus[2].bus_id = 2;
//b->i2c_bus[2].sda = 0;
//b->i2c_bus[2].scl = 0;
// 1 SPI bus
b->spi_bus_count = 1;
b->def_spi_bus = 0;
b->spi_bus[0].bus_id = 32766;
b->spi_bus[0].slave_s = 0;
//b->spi_bus[0].cs = 0;
//b->spi_bus[0].mosi = 0;
//b->spi_bus[0].miso = 0;
//b->spi_bus[0].sclk = 0;
// Arduino header UART (default)
b->uart_dev_count = 1;
b->def_uart_dev = 0;
b->uart_dev[0].device_path = "/dev/ttyS1";
//b->uart_dev[0].rx = 0;
//b->uart_dev[0].tx = 0;
return b;
}

6
src/arm/arm.c
View File

@@ -27,6 +27,7 @@
#include <string.h>
#include "arm/96boards.h"
#include "arm/altera_socfpga.h"
#include "arm/banana.h"
#include "arm/beaglebone.h"
#include "arm/phyboard.h"
@@ -70,6 +71,8 @@ mraa_arm_platform()
else if (mraa_file_exist("/sys/class/leds/green:ph24:led1")) {
platform_type = MRAA_BANANA;
}
} else if (strstr(line, "Altera SOCFPGA")) {
platform_type = MRAA_ALTERA_SOCFPGA;
}
}
}
@@ -107,6 +110,9 @@ mraa_arm_platform()
case MRAA_96BOARDS:
plat = mraa_96boards();
break;
case MRAA_ALTERA_SOCFPGA:
plat = mraa_altera_socfpga();
break;
default:
plat = NULL;
syslog(LOG_ERR, "Unknown Platform, currently not supported by MRAA");