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Enable CherryHills (Braswell) support for GPIO

Enable the GPIOs for Cherryhills (Braswell).

Signed-off-by: Karena Anum Kamaruzaman <karena.anum.kamaruzaman@intel.com>
Signed-off-by: Constantin Musca <constantin.musca@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
This commit is contained in:
Karena Anum Kamaruzaman
2016-01-22 17:02:58 +02:00
committed by Brendan Le Foll
parent 04f3b93f85
commit 084883c210
6 changed files with 152 additions and 1 deletions

View File

@@ -48,6 +48,7 @@ typedef enum {
MRAA_INTEL_NUC5 = 8, /**< The Intel 5th generations Broadwell NUCs */
MRAA_96BOARDS = 9, /**< Linaro 96boards */
MRAA_INTEL_SOFIA_3GR = 10, /**< The Intel SoFIA 3GR */
MRAA_INTEL_CHERRYHILLS = 11, /**< The Intel Braswell Cherryhills */
// USB platform extenders start at 256
MRAA_FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */