Enable CherryHills (Braswell) support for GPIO
Enable the GPIOs for Cherryhills (Braswell). Signed-off-by: Karena Anum Kamaruzaman <karena.anum.kamaruzaman@intel.com> Signed-off-by: Constantin Musca <constantin.musca@intel.com> Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
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Brendan Le Foll
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04f3b93f85
commit
084883c210
@@ -48,6 +48,7 @@ typedef enum {
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MRAA_INTEL_NUC5 = 8, /**< The Intel 5th generations Broadwell NUCs */
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MRAA_96BOARDS = 9, /**< Linaro 96boards */
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MRAA_INTEL_SOFIA_3GR = 10, /**< The Intel SoFIA 3GR */
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MRAA_INTEL_CHERRYHILLS = 11, /**< The Intel Braswell Cherryhills */
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// USB platform extenders start at 256
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MRAA_FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */
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