Enable CherryHills (Braswell) support for GPIO

Enable the GPIOs for Cherryhills (Braswell).

Signed-off-by: Karena Anum Kamaruzaman <karena.anum.kamaruzaman@intel.com>
Signed-off-by: Constantin Musca <constantin.musca@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>

Android.mk

@@ -35,7 +35,8 @@ LOCAL_SRC_FILES := \
     src/x86/intel_de3815.c \
     src/x86/intel_nuc5.c \
     src/x86/intel_sofia_3gr.c \
-    src/x86/intel_minnow_byt_compatible.c
+    src/x86/intel_minnow_byt_compatible.c \
+    src/x86/intel_cherryhills.c
 
 # glob.c pulled in from NetBSD project (BSD 3-clause License)
 LOCAL_SRC_FILES += \

api/mraa/types.h

@@ -48,6 +48,7 @@ typedef enum {
     MRAA_INTEL_NUC5 = 8,            /**< The Intel 5th generations Broadwell NUCs */
     MRAA_96BOARDS = 9,            /**< Linaro 96boards */
     MRAA_INTEL_SOFIA_3GR = 10,      /**< The Intel SoFIA 3GR */
+    MRAA_INTEL_CHERRYHILLS = 11,     /**< The Intel Braswell Cherryhills */
 
     // USB platform extenders start at 256
     MRAA_FTDI_FT4222 = 256,         /**< FTDI FT4222 USB to i2c bridge */

include/x86/intel_cherryhills.h

@@ -0,0 +1,41 @@
+/*
+ * Author: Karena Anum Kamaruzaman <karena.anum.kamaruzaman@intel.com>
+ * Copyright (c) 2016 Intel Corporation.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mraa_internal.h"
+
+// +1 as pins are "1 indexed"
+#define MRAA_INTEL_CHERRYHILLS_PINCOUNT (5 + 1)
+
+mraa_board_t*
+mraa_intel_cherryhills();
+
+#ifdef __cplusplus
+}
+#endif

src/CMakeLists.txt

@@ -28,6 +28,7 @@ set (mraa_LIB_X86_SRCS_NOAUTO
   ${PROJECT_SOURCE_DIR}/src/x86/intel_nuc5.c
   ${PROJECT_SOURCE_DIR}/src/x86/intel_minnow_byt_compatible.c
   ${PROJECT_SOURCE_DIR}/src/x86/intel_sofia_3gr.c
+  ${PROJECT_SOURCE_DIR}/src/x86/intel_cherryhills.c
 )
 
 message (INFO " - Adding support for platform ${MRAAPLATFORMFORCE}")
@@ -49,6 +50,8 @@ if (NOT ${MRAAPLATFORMFORCE} STREQUAL "ALL")
     set (mraa_LIB_X86_SRCS_NOAUTO ${PROJECT_SOURCE_DIR}/src/x86/x86.c ${PROJECT_SOURCE_DIR}/src/x86/intel_nuc5.c)
   elseif (${MRAAPLATFORMFORCE} STREQUAL "MRAA_INTEL_SOFIA_3GR")
     set (mraa_LIB_X86_SRCS_NOAUTO ${PROJECT_SOURCE_DIR}/src/x86/x86.c ${PROJECT_SOURCE_DIR}/src/x86/intel_sofia_3gr.c)
+  elseif (${MRAAPLATFORMFORCE} STREQUAL "MRAA_INTEL_CHERRYHILLS")
+    set (mraa_LIB_X86_SRCS_NOAUTO ${PROJECT_SOURCE_DIR}/src/x86/x86.c ${PROJECT_SOURCE_DIR}/src/x86/intel_cherryhills.c)
   else ()
     message (ERROR " - Unknown x86 platform enabled!")
   endif ()

src/x86/intel_cherryhills.c

@@ -0,0 +1,99 @@
+/*
+ * Author: Karena Anum Kamaruzaman <karena.anum.kamaruzaman@intel.com>
+ * Copyright (c) 2016 Intel Corporation.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+
+#include "common.h"
+#include "x86/intel_cherryhills.h"
+
+#define PLATFORM_NAME "Braswell Cherry Hill"
+
+mraa_board_t*
+mraa_intel_cherryhills()
+{
+    mraa_board_t* b = (mraa_board_t*) calloc(1, sizeof(mraa_board_t));
+    if (b == NULL) {
+        return NULL;
+    }
+
+    b->platform_name = PLATFORM_NAME;
+    b->phy_pin_count = MRAA_INTEL_CHERRYHILLS_PINCOUNT;
+    b->aio_count = 0;
+    b->adc_raw = 0;
+    b->adc_supported = 0;
+
+    b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t) * MRAA_INTEL_CHERRYHILLS_PINCOUNT);
+    if (b->pins == NULL) {
+        goto error;
+    }
+
+    b->adv_func = (mraa_adv_func_t*) calloc(1, sizeof(mraa_adv_func_t));
+    if (b->adv_func == NULL) {
+        free(b->pins);
+        goto error;
+    }
+
+    int pos = 0;
+    //Physical header where these pins are: J3E5
+    strncpy(b->pins[pos].name, "GSUS6", 8);
+    b->pins[pos].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
+    b->pins[pos].gpio.pinmap = 416;
+    b->pins[pos].gpio.mux_total = 0;
+    pos++;
+
+    strncpy(b->pins[pos].name, "GSUS8", 8);
+    b->pins[pos].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
+    b->pins[pos].gpio.pinmap = 409;
+    b->pins[pos].gpio.mux_total = 0;
+    pos++;
+
+    strncpy(b->pins[pos].name, "GSUS7", 8);
+    b->pins[pos].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
+    b->pins[pos].gpio.pinmap = 414;
+    b->pins[pos].gpio.mux_total = 0;
+    pos++;
+
+    //Physical header where these pins are: J3E3
+    strncpy(b->pins[pos].name, "GSUS0", 8);
+    b->pins[pos].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
+    b->pins[pos].gpio.pinmap = 406;
+    b->pins[pos].gpio.mux_total = 0;
+    pos++;
+
+    strncpy(b->pins[pos].name, "GSUS1", 8);
+    b->pins[pos].capabilites = (mraa_pincapabilities_t){ 1, 1, 0, 0, 0, 0, 0, 0 };
+    b->pins[pos].gpio.pinmap = 410;
+    b->pins[pos].gpio.mux_total = 0;
+    pos++;
+
+    return b;
+error:
+    syslog(LOG_CRIT, "Cherryhills(Braswell): Platform failed to initialise");
+    free(b);
+    return NULL;
+}

src/x86/x86.c

@@ -35,6 +35,7 @@
 #include "x86/intel_nuc5.h"
 #include "x86/intel_minnow_byt_compatible.h"
 #include "x86/intel_sofia_3gr.h"
+#include "x86/intel_cherryhills.h"
 
 mraa_platform_t
 mraa_x86_platform()
@@ -78,6 +79,9 @@ mraa_x86_platform()
             } else if (strncasecmp(line, "MinnowBoard Turbot", 18) == 0) {
                 platform_type = MRAA_INTEL_MINNOWBOARD_MAX;
                 plat = mraa_intel_minnowboard_byt_compatible(1);
+            } else if (strncasecmp(line, "Braswell Cherry Hill", 20) == 0) {
+                platform_type = MRAA_INTEL_CHERRYHILLS;
+                plat = mraa_intel_cherryhills();
             } else {
                 syslog(LOG_ERR, "Platform not supported, not initialising");
                 platform_type = MRAA_UNKNOWN_PLATFORM;
@@ -114,6 +118,8 @@ mraa_x86_platform()
     plat = mraa_intel_nuc5();
     #elif defined(xMRAA_INTEL_SOFIA_3GR)
     plat = mraa_intel_sofia_3gr();
+    #elif defined(xMRAA_INTEL_CHERRYHILLS)
+    plat = mraa_intel_cherryhills();
     #else
         #error "Not using a valid platform value from mraa_platform_t - cannot compile"
     #endif