Raspberries/mraa
Private
Public Access
2
0
Fork 0
Code Activity

joule: align SPI bus numbering with reality

Browse Source 
Also update docs to make the numbering and pins used crystal clear.

Closes #758.

Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
This commit is contained in:
Alex Tereschenko
2017-06-15 20:49:18 +02:00
parent 000746c20d
commit 32196d10e9
2 changed files with 22 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

32
docs/joule.md
View File

@@ -14,26 +14,22 @@ Interface notes
**SPI**
Two SPI buses are available, with one chipselect each. Pins listed are MRAA
numbered pins. Other chip selects are available if enabled in BIOS/EEPROM but
cannot be enabled as BIOS options. You will need the spidev kernel module
loaded, Ostro-XT and ref-os-iot does this by default.
Two SPI buses are available, one with three and another one with two chipselects.
In MRAA terms an SPI "bus" (denoted by a number) is a combination
of an actual bus + specific chipselect on this bus. In view of that + taking
into account that SPI1CS1 is not available on the board, in MRAA the above
translates into five available bus numbers - from 0 to 4, covering SPI0CS0 to SPI1CS2.
Bus 0 (32765)
MOSI = 4
MISO = 2
CS = 6
CLK = 10
Pins listed are MRAA numbered pins. You will need the `spidev` kernel module loaded
with appropriate board configuration for binding, Ref-OS-IoT does not enable this by default.
Bus 1 (32766)
MOSI = 67
MISO = 69
CS0 = 59
CS1 = 61
CLK = 65
(remove 40 from numbers to get pin header number for pins on low speed header
2)
MRAA bus # | Ref-OS-IoT bus # | Joule docs bus # | MOSI | MISO | CLK | CS
-----------|------------------|------------------|------|------|-----|----
0 | 32766 | SPI0 | 67 (J13-27)| 69 (J13-29) | 65 (J13-25) | 59 (J13-19)
1 | 32766 | SPI0 | 67 (J13-27)| 69 (J13-29) | 65 (J13-25) | 61 (J13-21)
2 | 32766 | SPI0 | 67 (J13-27)| 69 (J13-29) | 65 (J13-25) | 63 (J13-23)
3 | 32765 | SPI1 | 4 (J12-4)| 2 (J12-2) | 10 (J12-10) | 6 (J12-6)
4 | 32765 | SPI1 | 4 (J12-4)| 2 (J12-2) | 10 (J12-10) | 8 (J12-8)
**UART** Some pins are labelled as UARTs but are not configured in BIOS as UART
so only available UART is on the FTDI header. Disable the getty on ttyS2 and

12
src/x86/intel_joule_expansion.c
View File

@@ -136,14 +136,18 @@ mraa_joule_expansion_board()
b->def_i2c_bus = b->i2c_bus[0].bus_id;
b->spi_bus_count = 3;
b->spi_bus_count = 5;
b->def_spi_bus = 0;
b->spi_bus[0].bus_id = 32765;
b->spi_bus[0].bus_id = 32766;
b->spi_bus[0].slave_s = 0;
b->spi_bus[1].bus_id = 32766;
b->spi_bus[1].slave_s = 0;
b->spi_bus[1].slave_s = 1;
b->spi_bus[2].bus_id = 32766;
b->spi_bus[2].slave_s = 1;
b->spi_bus[2].slave_s = 2;
b->spi_bus[3].bus_id = 32765;
b->spi_bus[3].slave_s = 0;
b->spi_bus[4].bus_id = 32765;
b->spi_bus[4].slave_s = 2;
int pos = 0;