joule: align SPI bus numbering with reality
Also update docs to make the numbering and pins used crystal clear. Closes #758. Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
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@@ -14,26 +14,22 @@ Interface notes
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**SPI**
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Two SPI buses are available, with one chipselect each. Pins listed are MRAA
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numbered pins. Other chip selects are available if enabled in BIOS/EEPROM but
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cannot be enabled as BIOS options. You will need the spidev kernel module
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loaded, Ostro-XT and ref-os-iot does this by default.
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Two SPI buses are available, one with three and another one with two chipselects.
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In MRAA terms an SPI "bus" (denoted by a number) is a combination
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of an actual bus + specific chipselect on this bus. In view of that + taking
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into account that SPI1CS1 is not available on the board, in MRAA the above
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translates into five available bus numbers - from 0 to 4, covering SPI0CS0 to SPI1CS2.
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Bus 0 (32765)
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MOSI = 4
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MISO = 2
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CS = 6
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CLK = 10
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Pins listed are MRAA numbered pins. You will need the `spidev` kernel module loaded
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with appropriate board configuration for binding, Ref-OS-IoT does not enable this by default.
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Bus 1 (32766)
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MOSI = 67
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MISO = 69
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CS0 = 59
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CS1 = 61
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CLK = 65
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(remove 40 from numbers to get pin header number for pins on low speed header
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2)
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MRAA bus # | Ref-OS-IoT bus # | Joule docs bus # | MOSI | MISO | CLK | CS
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-----------|------------------|------------------|------|------|-----|----
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0 | 32766 | SPI0 | 67 (J13-27)| 69 (J13-29) | 65 (J13-25) | 59 (J13-19)
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1 | 32766 | SPI0 | 67 (J13-27)| 69 (J13-29) | 65 (J13-25) | 61 (J13-21)
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2 | 32766 | SPI0 | 67 (J13-27)| 69 (J13-29) | 65 (J13-25) | 63 (J13-23)
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3 | 32765 | SPI1 | 4 (J12-4)| 2 (J12-2) | 10 (J12-10) | 6 (J12-6)
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4 | 32765 | SPI1 | 4 (J12-4)| 2 (J12-2) | 10 (J12-10) | 8 (J12-8)
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**UART** Some pins are labelled as UARTs but are not configured in BIOS as UART
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so only available UART is on the FTDI header. Disable the getty on ttyS2 and
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