Raspberries/mraa
Private
Public Access
2
0
Fork 0
Code Activity

platform: add Radxa CM3 platform support

Browse Source 
Signed-off-by: Nascs <nascs@radxa.com>
Co-authored-by: ZHANG Yuntian <yt@radxa.com>
This commit is contained in:
nascs
2023-10-08 03:05:17 +00:00
committed by Tom Ingleby
parent 81ece69655
commit 651131b475
10 changed files with 332 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
README.md
View File

@@ -45,6 +45,7 @@ ARM
* [phyBOARD-Wega](../master/docs/phyboard-wega.md)
* [96Boards](../master/docs/96boards.md)
* [ADLINK IPi-SMARC ARM](../master/docs/adlink_ipi_arm.md)
* [Radxa CM3](../master/docs/radxa_cm3.md)
* [Radxa ROCK 3B](../master/docs/radxa_rock_3b.md)
* [Radxa ROCK 3C](../master/docs/radxa_rock_3c.md)
* [Radxa ROCK 5A](../master/docs/radxa_rock_5a.md)

34
api/mraa/types.h
View File

@@ -75,6 +75,7 @@ typedef enum {
MRAA_RADXA_ROCK_5B = 30, /**< Radxa ROCK 5 Model B */
MRAA_ORANGE_PI_PRIME = 31, /**< Orange Pi Prime board */
MRAA_RADXA_ROCK_3B = 32, /**< Radxa ROCK 3 Model B */
MRAA_RADXA_CM3 = 33, /**< Radxa CM3 */
// USB platform extenders start at 256
MRAA_FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */
@@ -316,6 +317,39 @@ typedef enum {
MRAA_RADXA_ROCK_3C_PIN40 = 40
} mraa_radxa_rock_3c_wiring_t;
/**
* Radxa CM3 IO GPIO numbering enum
*/
typedef enum {
MRAA_RADXA_CM3_IO_PIN3 = 3,
MRAA_RADXA_CM3_IO_PIN5 = 5,
MRAA_RADXA_CM3_IO_PIN7 = 7,
MRAA_RADXA_CM3_IO_PIN8 = 8,
MRAA_RADXA_CM3_IO_PIN10 = 10,
MRAA_RADXA_CM3_IO_PIN11 = 11,
MRAA_RADXA_CM3_IO_PIN12 = 12,
MRAA_RADXA_CM3_IO_PIN13 = 13,
MRAA_RADXA_CM3_IO_PIN15 = 15,
MRAA_RADXA_CM3_IO_PIN16 = 16,
MRAA_RADXA_CM3_IO_PIN18 = 18,
MRAA_RADXA_CM3_IO_PIN19 = 19,
MRAA_RADXA_CM3_IO_PIN21 = 21,
MRAA_RADXA_CM3_IO_PIN22 = 22,
MRAA_RADXA_CM3_IO_PIN23 = 23,
MRAA_RADXA_CM3_IO_PIN24 = 24,
MRAA_RADXA_CM3_IO_PIN27 = 27,
MRAA_RADXA_CM3_IO_PIN28 = 28,
MRAA_RADXA_CM3_IO_PIN29 = 29,
MRAA_RADXA_CM3_IO_PIN31 = 31,
MRAA_RADXA_CM3_IO_PIN32 = 32,
MRAA_RADXA_CM3_IO_PIN33 = 33,
MRAA_RADXA_CM3_IO_PIN35 = 35,
MRAA_RADXA_CM3_IO_PIN36 = 36,
MRAA_RADXA_CM3_IO_PIN37 = 37,
MRAA_RADXA_CM3_IO_PIN38 = 38,
MRAA_RADXA_CM3_IO_PIN40 = 40
} mraa_radxa_cm3_io_wiring_t;
/**
* ROCKPI4 GPIO numbering enum
*/

34
api/mraa/types.hpp
View File

@@ -69,6 +69,7 @@ typedef enum {
RADXA_ROCK_5B = 30, /**< Radxa ROCK 5 Model B */
ORANGE_PI_PRIME = 31, /**< Orange Pi Prime board */
RADXA_ROCK_3B = 32, /**< Radxa ROCK 3 Model B */
RADXA_CM3 = 33, /**< Radxa CM3 */
FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */
@@ -306,6 +307,39 @@ typedef enum {
RADXA_ROCK_3C_PIN40 = 40
} RadxaRock3CWiring;
/**
* Radxa CM3 IO GPIO numbering enum
*/
typedef enum {
RADXA_CM3_IO_PIN3 = 3,
RADXA_CM3_IO_PIN5 = 5,
RADXA_CM3_IO_PIN7 = 7,
RADXA_CM3_IO_PIN8 = 8,
RADXA_CM3_IO_PIN10 = 10,
RADXA_CM3_IO_PIN11 = 11,
RADXA_CM3_IO_PIN12 = 12,
RADXA_CM3_IO_PIN13 = 13,
RADXA_CM3_IO_PIN15 = 15,
RADXA_CM3_IO_PIN16 = 16,
RADXA_CM3_IO_PIN18 = 18,
RADXA_CM3_IO_PIN19 = 19,
RADXA_CM3_IO_PIN21 = 21,
RADXA_CM3_IO_PIN22 = 22,
RADXA_CM3_IO_PIN23 = 23,
RADXA_CM3_IO_PIN24 = 24,
RADXA_CM3_IO_PIN27 = 27,
RADXA_CM3_IO_PIN28 = 28,
RADXA_CM3_IO_PIN29 = 29,
RADXA_CM3_IO_PIN31 = 31,
RADXA_CM3_IO_PIN32 = 32,
RADXA_CM3_IO_PIN33 = 33,
RADXA_CM3_IO_PIN35 = 35,
RADXA_CM3_IO_PIN36 = 36,
RADXA_CM3_IO_PIN37 = 37,
RADXA_CM3_IO_PIN38 = 38,
RADXA_CM3_IO_PIN40 = 40
} RadxaCM3IOWiring;
/**
* ROCKPI4 GPIO numbering enum
*/

6
docs/index.java.md
View File

@@ -54,6 +54,12 @@ Specific platform information for supported platforms is documented here:
- @ref iei-tank
- @ref up-xtreme
- @ref _orange_pi_prime
- @ref radxa_cm3
- @ref radxa_rock_3b
- @ref radxa_rock_3c
- @ref radxa_rock_5a
- @ref radxa_rock_5b
- @ref rockpi4
## DEBUGGING

6
docs/index.md
View File

@@ -62,6 +62,12 @@ Specific platform information for supported platforms is documented here:
- @ref iei-tank
- @ref upXtreme
- @ref _orange_pi_prime
- @ref radxa_cm3
- @ref radxa_rock_3b
- @ref radxa_rock_3c
- @ref radxa_rock_5a
- @ref radxa_rock_5b
- @ref rockpi4
## DEBUGGING

48
docs/radxa_cm3.md Normal file
View File

@@ -0,0 +1,48 @@
Radxa CM3 {#_Radxa}
=========
The Radxa CM3 is a System on Module (SoM) based on the Rockchip RK3566 System on Chip (SoC). CM3 integrates the Central Process Unit (CPU), Power Management Unit (PMU), DRAM memory, flash storage and wireless connectivity (WiFi 5 and BT 5.0) in a small form factor of just 55mm x 40mm. CM3 uses 3x 100P 0.4mm-pitch Board-to-Board connectors to export various features, and can be combined with the customer's baseboard to build complete products, thereby speeding up the research and development process.
Currently, CM3 is compatible with Radxa CM3 IO Board and Raspberry Pi CM4 IO Board.
Interface notes
---------------
- UART2 is enabled as the default console.
- All UART ports support baud up to 1500000.
Pin Mapping
-----------
Radxa CM3 IO Board and Raspberry Pi CM4 IO Baseboard's 40-pin expansion header are compatible. The following pinout applies to both products:
| Function3| Function3| Function2| Function1| PIN | PIN | Function1| Function2| Function3|
|-------------|------------|-------------|----------|:------|------:|-----------|-------------|----------|
| | | | 3V3| 1 | 2 | +5.0V| | |
| PWM2_M1|SPI0_MOSI_M0| I2C2_SDA_M0| GPIO0_B6| 3 | 4 | +5.0V| | |
| PWM1_M1| SPI0_CLK_M0| I2C2_SCL_M0| GPIO0_B5| 5 | 6 | GND| | |
| | | | GPIO3_D5| 7 | 8 | GPIO0_D1| UART2_TX_M0| |
| | | | GND| 9 | 10 | GPIO0_D0| UART2_RX_M0| |
| | | PWM0_M1| GPIO0_C7| 11 | 12 | GPIO3_C7| | |
| | | PWM0_M0| GPIO0_B7| 13 | 14 | GND| | |
| | | PWM4| GPIO0_C3| 15 | 16 | GPIO3_D4| | |
| | | | +3.3V| 17 | 18 | GPIO3_D3| | |
| | I2C4_SDA_M0| SPI3_MOSI_M0| GPIO4_B2| 19 | 20 | GND| | |
| | | SPI3_MISO_M0| GPIO4_B0| 21 | 22 | GPIO3_C6| | |
| | I2C4_SCL_M0| SPI3_CLK_M0| GPIO4_B3| 23 | 24 | GPIO4_A6| SPI3_CS0_M0| |
| | | | GND| 25 | 26 |SARADC_VIN3| | |
| | | I2C2_SDA_M1| GPIO4_B4| 27 | 28 | GPIO4_B5| I2C2_SCL_M1| |
| | | | GPIO4_B1| 29 | 30 | GND| | |
| | PWM6| SPI0_MISO_M0| GPIO0_C5| 31 | 32 | GPIO4_C0| UART5_TX_M1| |
| | PWM7_IR| SPI0_CS0_M0| GPIO0_C6| 33 | 34 | GND| | |
| | | | GPIO3_D0| 35 | 36 | GPIO4_A7| SPI3_CS1_M0| |
| | | PWM3_IR| GPIO0_C2| 37 | 38 | GPIO3_D2| | |
| | | | GND| 39 | 40 | GPIO3_D1| | |
Supports
--------
You can find additional product support in the following channels:
- [Product Info](https://docs.radxa.com/en/compute-module/cm3)
- [Forums](https://forum.radxa.com/c/rock3)
- [Github](https://github.com/radxa)

32
include/arm/radxa_cm3.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* Author: Nascs <nascs@radxa.com>
* Copyright (c) 2023 Radxa Limited.
*
* SPDX-License-Identifier: MIT
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "mraa_internal.h"
#define MRAA_RADXA_CM3_GPIO_COUNT 28
#define MRAA_RADXA_CM3_I2C_COUNT 3
#define MRAA_RADXA_CM3_SPI_COUNT 2
#define MRAA_RADXA_CM3_UART_COUNT 1
#define MRAA_RADXA_CM3_PWM_COUNT 9
#define MRAA_RADXA_CM3_AIO_COUNT 1
#define MRAA_RADXA_CM3_PIN_COUNT 40
#define PLATFORM_NAME_RADXA_CM3_IO "Radxa Compute Module 3(CM3) IO Board"
#define PLATFORM_NAME_RADXA_CM3_IO_2 "Radxa CM3 IO Board"
#define PLATFORM_NAME_RADXA_CM3_RPI_CM4_IO "Radxa CM3 RPI CM4 IO" // The core board of the Radxa CM3 is compatible with the RPI CM4 IO backplane.
mraa_board_t *
mraa_radxa_cm3();
#ifdef __cplusplus
}
#endif

1
src/CMakeLists.txt
View File

@@ -109,6 +109,7 @@ set (mraa_LIB_ARM_SRCS_NOAUTO
${PROJECT_SOURCE_DIR}/src/arm/de_nano_soc.c
${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_3b.c
${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_3c.c
${PROJECT_SOURCE_DIR}/src/arm/radxa_cm3.c
${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_5a.c
${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_5b.c
${PROJECT_SOURCE_DIR}/src/arm/rockpi4.c

8
src/arm/arm.c
View File

@@ -10,6 +10,7 @@
#include <string.h>
#include "arm/96boards.h"
#include "arm/radxa_cm3.h"
#include "arm/radxa_rock_3b.h"
#include "arm/radxa_rock_3c.h"
#include "arm/radxa_rock_5a.h"
@@ -96,6 +97,10 @@ mraa_arm_platform()
platform_type = MRAA_96BOARDS;
else if (mraa_file_contains("/proc/device-tree/model", "Avnet Ultra96 Rev1"))
platform_type = MRAA_96BOARDS;
else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_CM3_IO) ||
mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_CM3_IO_2) ||
mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_CM3_RPI_CM4_IO))
platform_type = MRAA_RADXA_CM3;
else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_ROCK_3B))
platform_type = MRAA_RADXA_ROCK_3B;
else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_ROCK_3C))
@@ -135,6 +140,9 @@ mraa_arm_platform()
case MRAA_96BOARDS:
plat = mraa_96boards();
break;
case MRAA_RADXA_CM3:
plat = mraa_radxa_cm3();
break;
case MRAA_RADXA_ROCK_3B:
plat = mraa_radxa_rock_3b();
break;

161
src/arm/radxa_cm3.c Normal file
View File

@@ -0,0 +1,161 @@
/*
* Author: Nascs <nascs@radxa.com>
* Copyright (c) 2023 Radxa Limited.
*
* SPDX-License-Identifier: MIT
*/
#include <mraa/common.h>
#include <stdarg.h>
#include <stdlib.h>
#include <string.h>
#include <sys/mman.h>
#include "arm/radxa_cm3.h"
#include "common.h"
const char* radxa_cm3_serialdev[MRAA_RADXA_CM3_UART_COUNT] = { "/dev/ttyS2" };
void
mraa_radxa_cm3_pininfo(mraa_board_t* board, int index, int gpio_chip, int gpio_line, mraa_pincapabilities_t pincapabilities_t, char* pin_name)
{
if (index > board->phy_pin_count)
return;
mraa_pininfo_t* pininfo = &board->pins[index];
strncpy(pininfo->name, pin_name, MRAA_PIN_NAME_SIZE);
if (pincapabilities_t.gpio == 1) {
pininfo->gpio.gpio_chip = gpio_chip;
pininfo->gpio.gpio_line = gpio_line;
}
pininfo->capabilities = pincapabilities_t;
pininfo->gpio.mux_total = 0;
}
mraa_board_t*
mraa_radxa_cm3()
{
mraa_board_t* b = (mraa_board_t*) calloc(1, sizeof(mraa_board_t));
if (b == NULL) {
return NULL;
}
b->adv_func = (mraa_adv_func_t*) calloc(1, sizeof(mraa_adv_func_t));
if (b->adv_func == NULL) {
free(b);
return NULL;
}
// pin mux for buses are setup by default by kernel so tell mraa to ignore them
b->no_bus_mux = 1;
b->phy_pin_count = MRAA_RADXA_CM3_PIN_COUNT + 1;
if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_CM3_IO) ||
mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_CM3_IO_2)) {
b->platform_name = PLATFORM_NAME_RADXA_CM3_IO_2;
} else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_CM3_RPI_CM4_IO)) {
b->platform_name = PLATFORM_NAME_RADXA_CM3_RPI_CM4_IO;
} else {
printf("An unknown product detected. Fail early...\n");
exit(-1);
}
b->chardev_capable = 1;
// UART
b->uart_dev_count = MRAA_RADXA_CM3_UART_COUNT;
b->def_uart_dev = 0;
b->uart_dev[0].index = 2;
b->uart_dev[0].device_path = (char*) radxa_cm3_serialdev[0];
// I2C
b->i2c_bus_count = MRAA_RADXA_CM3_I2C_COUNT;
b->def_i2c_bus = 0;
b->i2c_bus[0].bus_id = 2;
b->i2c_bus[1].bus_id = 4;
// SPI
b->spi_bus_count = MRAA_RADXA_CM3_SPI_COUNT;
b->def_spi_bus = 0;
b->spi_bus[0].bus_id = 0;
b->spi_bus[1].bus_id = 3;
// PWM
b->pwm_dev_count = MRAA_RADXA_CM3_PWM_COUNT;
b->pwm_default_period = 500;
b->pwm_max_period = 2147483;
b->pwm_min_period = 1;
b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t) * b->phy_pin_count);
if (b->pins == NULL) {
free(b->adv_func);
free(b);
return NULL;
}
b->pins[13].pwm.parent_id = 0; // pwm0-m0
b->pins[13].pwm.mux_total = 0;
b->pins[11].pwm.parent_id = 0; // pwm0-m1
b->pins[11].pwm.mux_total = 0;
b->pins[5].pwm.parent_id = 1; // pwm1-m1
b->pins[5].pwm.mux_total = 0;
b->pins[3].pwm.parent_id = 2; // pwm2-m1
b->pins[3].pwm.mux_total = 0;
b->pins[37].pwm.parent_id = 3; // pwm3
b->pins[37].pwm.mux_total = 0;
b->pins[15].pwm.parent_id = 4; // pwm4
b->pins[15].pwm.mux_total = 0;
b->pins[31].pwm.parent_id = 6; // pwm6
b->pins[31].pwm.mux_total = 0;
b->pins[33].pwm.parent_id = 15; // pwm7
b->pins[33].pwm.mux_total = 0;
b->pins[32].pwm.parent_id = 11; // pwm11-m1
b->pins[32].pwm.mux_total = 0;
mraa_radxa_cm3_pininfo(b, 0, -1, -1, (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, "INVALID");
mraa_radxa_cm3_pininfo(b, 1, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3.3V");
mraa_radxa_cm3_pininfo(b, 2, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "5.0V");
mraa_radxa_cm3_pininfo(b, 3, 0, 14, (mraa_pincapabilities_t){1,1,1,0,1,1,0,0}, "GPIO0_B6");
mraa_radxa_cm3_pininfo(b, 4, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "5.0V");
mraa_radxa_cm3_pininfo(b, 5, 0, 13, (mraa_pincapabilities_t){1,1,1,0,1,1,0,0}, "GPIO0_B5");
mraa_radxa_cm3_pininfo(b, 6, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_cm3_pininfo(b, 7, 3, 29, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_D5");
mraa_radxa_cm3_pininfo(b, 8, 0, 25, (mraa_pincapabilities_t){1,0,0,0,0,0,0,1}, "GPIO0_D1"); // GPIO0_D1 was used by fiq_debugger, function GPIO cannot be enabled
mraa_radxa_cm3_pininfo(b, 9, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_cm3_pininfo(b, 10, 0, 24, (mraa_pincapabilities_t){1,0,0,0,0,0,0,1}, "GPIO0_D0"); // GPIO0_D0 was used by fiq_debugger, function GPIO cannot be enabled
mraa_radxa_cm3_pininfo(b, 11, 0, 23, (mraa_pincapabilities_t){1,1,1,0,0,0,0,0}, "GPIO0_C7");
mraa_radxa_cm3_pininfo(b, 12, 3, 23, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_C7");
mraa_radxa_cm3_pininfo(b, 13, 0 ,15, (mraa_pincapabilities_t){1,1,1,0,0,0,0,0}, "GPIO0_B7");
mraa_radxa_cm3_pininfo(b, 14, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_cm3_pininfo(b, 15, 0, 19, (mraa_pincapabilities_t){1,1,1,0,0,0,0,0}, "GPIO0_C3");
mraa_radxa_cm3_pininfo(b, 16, 3, 28, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_D4");
mraa_radxa_cm3_pininfo(b, 17, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3.3V");
mraa_radxa_cm3_pininfo(b, 18, 3, 27, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_D3");
mraa_radxa_cm3_pininfo(b, 19, 4, 10, (mraa_pincapabilities_t){1,1,0,0,1,1,0,0}, "GPIO4_B2");
mraa_radxa_cm3_pininfo(b, 20, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_cm3_pininfo(b, 21, 4, 8, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO4_B0");
mraa_radxa_cm3_pininfo(b, 22, 3, 22, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_C6");
mraa_radxa_cm3_pininfo(b, 23, 4, 11, (mraa_pincapabilities_t){1,1,0,0,1,1,0,0}, "GPIO4_B3");
mraa_radxa_cm3_pininfo(b, 24, 4, 6, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO4_A6");
mraa_radxa_cm3_pininfo(b, 25, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_cm3_pininfo(b, 26, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,1,0}, "SARADC_VIN3");
mraa_radxa_cm3_pininfo(b, 27, 4, 12, (mraa_pincapabilities_t){1,1,0,0,0,1,0,0}, "GPIO4_B4");
mraa_radxa_cm3_pininfo(b, 28, 4, 13, (mraa_pincapabilities_t){1,1,0,0,0,1,0,0}, "GPIO4_B5");
mraa_radxa_cm3_pininfo(b, 29, 4, 9, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO4_B1");
mraa_radxa_cm3_pininfo(b, 30, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_cm3_pininfo(b, 31, 0, 21, (mraa_pincapabilities_t){1,1,1,0,1,0,0,0}, "GPIO0_C5");
mraa_radxa_cm3_pininfo(b, 32, 4, 16, (mraa_pincapabilities_t){1,1,1,0,0,0,0,0}, "GPIO4_C0");
mraa_radxa_cm3_pininfo(b, 33, 0, 22, (mraa_pincapabilities_t){1,1,1,0,1,0,0,0}, "GPIO0_C6");
mraa_radxa_cm3_pininfo(b, 34, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_cm3_pininfo(b, 35, 3, 24, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_D0");
mraa_radxa_cm3_pininfo(b, 36, 4, 7, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO4_A7");
mraa_radxa_cm3_pininfo(b, 37, 0, 18, (mraa_pincapabilities_t){1,1,1,0,0,0,0,0}, "GPIO0_C2");
mraa_radxa_cm3_pininfo(b, 38, 3, 26, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_D2");
mraa_radxa_cm3_pininfo(b, 39, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_cm3_pininfo(b, 40, 3, 25, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_D1");
return b;
}