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platform: add Radxa ROCK 3B platform support

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Signed-off-by: Nascs <nascs@radxa.com>
This commit is contained in:
nascs
2023-10-07 09:21:09 +00:00
committed by Tom Ingleby
parent f727c01d2e
commit 81ece69655
8 changed files with 319 additions and 0 deletions
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1
README.md
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@@ -45,6 +45,7 @@ ARM
* [phyBOARD-Wega](../master/docs/phyboard-wega.md)
* [96Boards](../master/docs/96boards.md)
* [ADLINK IPi-SMARC ARM](../master/docs/adlink_ipi_arm.md)
* [Radxa ROCK 3B](../master/docs/radxa_rock_3b.md)
* [Radxa ROCK 3C](../master/docs/radxa_rock_3c.md)
* [Radxa ROCK 5A](../master/docs/radxa_rock_5a.md)
* [Radxa ROCK 5B](../master/docs/radxa_rock_5b.md)

34
api/mraa/types.h
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@@ -74,6 +74,7 @@ typedef enum {
MRAA_RADXA_ROCK_5A = 29, /**< Radxa ROCK 5 Model A */
MRAA_RADXA_ROCK_5B = 30, /**< Radxa ROCK 5 Model B */
MRAA_ORANGE_PI_PRIME = 31, /**< Orange Pi Prime board */
MRAA_RADXA_ROCK_3B = 32, /**< Radxa ROCK 3 Model B */
// USB platform extenders start at 256
MRAA_FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */
@@ -249,6 +250,39 @@ typedef enum {
MRAA_RADXA_ROCK_5B_PIN40 = 40
} mraa_radxa_rock_5b_wiring_t;
/**
* Radxa ROCK 3 Model B GPIO numbering enum
*/
typedef enum {
RADXA_ROCK_3B_PIN3 = 3,
RADXA_ROCK_3B_PIN5 = 5,
RADXA_ROCK_3B_PIN7 = 7,
RADXA_ROCK_3B_PIN8 = 8,
RADXA_ROCK_3B_PIN10 = 10,
RADXA_ROCK_3B_PIN11 = 11,
RADXA_ROCK_3B_PIN12 = 12,
RADXA_ROCK_3B_PIN13 = 13,
RADXA_ROCK_3B_PIN15 = 15,
RADXA_ROCK_3B_PIN16 = 16,
RADXA_ROCK_3B_PIN18 = 18,
RADXA_ROCK_3B_PIN19 = 19,
RADXA_ROCK_3B_PIN21 = 21,
RADXA_ROCK_3B_PIN22 = 22,
RADXA_ROCK_3B_PIN23 = 23,
RADXA_ROCK_3B_PIN24 = 24,
RADXA_ROCK_3B_PIN27 = 27,
RADXA_ROCK_3B_PIN28 = 28,
RADXA_ROCK_3B_PIN29 = 29,
RADXA_ROCK_3B_PIN31 = 31,
RADXA_ROCK_3B_PIN32 = 32,
RADXA_ROCK_3B_PIN33 = 33,
RADXA_ROCK_3B_PIN35 = 35,
RADXA_ROCK_3B_PIN36 = 36,
RADXA_ROCK_3B_PIN38 = 38,
RADXA_ROCK_3B_PIN40 = 40
} mraa_radxa_rock_3b_wiring_t;
/**
* Radxa ROCK 3 Model C GPIO numbering enum
*/

33
api/mraa/types.hpp
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@@ -68,6 +68,7 @@ typedef enum {
RADXA_ROCK_5A = 29, /**< Radxa ROCK 5 Model A */
RADXA_ROCK_5B = 30, /**< Radxa ROCK 5 Model B */
ORANGE_PI_PRIME = 31, /**< Orange Pi Prime board */
RADXA_ROCK_3B = 32, /**< Radxa ROCK 3 Model B */
FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */
@@ -240,6 +241,38 @@ typedef enum {
RADXA_ROCK_5B_PIN40 = 40
} RadxaRock5BWiring;
/**
* Radxa ROCK 3 Model B GPIO numbering enum
*/
typedef enum {
RADXA_ROCK_3B_PIN3 = 3,
RADXA_ROCK_3B_PIN5 = 5,
RADXA_ROCK_3B_PIN7 = 7,
RADXA_ROCK_3B_PIN8 = 8,
RADXA_ROCK_3B_PIN10 = 10,
RADXA_ROCK_3B_PIN11 = 11,
RADXA_ROCK_3B_PIN12 = 12,
RADXA_ROCK_3B_PIN13 = 13,
RADXA_ROCK_3B_PIN15 = 15,
RADXA_ROCK_3B_PIN16 = 16,
RADXA_ROCK_3B_PIN18 = 18,
RADXA_ROCK_3B_PIN19 = 19,
RADXA_ROCK_3B_PIN21 = 21,
RADXA_ROCK_3B_PIN22 = 22,
RADXA_ROCK_3B_PIN23 = 23,
RADXA_ROCK_3B_PIN24 = 24,
RADXA_ROCK_3B_PIN27 = 27,
RADXA_ROCK_3B_PIN28 = 28,
RADXA_ROCK_3B_PIN29 = 29,
RADXA_ROCK_3B_PIN31 = 31,
RADXA_ROCK_3B_PIN32 = 32,
RADXA_ROCK_3B_PIN33 = 33,
RADXA_ROCK_3B_PIN35 = 35,
RADXA_ROCK_3B_PIN36 = 36,
RADXA_ROCK_3B_PIN38 = 38,
RADXA_ROCK_3B_PIN40 = 40
} RadxaRock3BWiring;
/**
* Radxa ROCK 3 Model C GPIO numbering enum
*/

48
docs/radxa_rock_3b.md Normal file
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@@ -0,0 +1,48 @@
Radxa ROCK 3 Model B {#_Radxa}
====================
Radxa ROCK 3 Model B is a Rockchip RK3568 based SBC(Single Board Computer) by Radxa. It can run Android or Linux. Radxa ROCK 3 Model B features a four core ARM processor, 64bit dual channel 3200Mb/s LPDDR4, HDMI up to 4K60p, MIPI DSI, MIPI CSI, 3.5mm combo audio jack, Wi-Fi 6, Bluetooth 5.0, USB, GbE LAN, and 40-pin color expansion header. Radxa ROCK 3 Model B is powered by the USB Type-C port, and supports 5V input only. The recommended power adapter is 5V/3A without SSD, or 5V/5A with SSD.
Interface notes
---------------
- UART2 is enabled as the default console.
- All UART ports support baud up to 1500000.
- Pin 3 and Pin 5 were used by audiopwm.
Pin Mapping
-----------
Radxa ROCK 3 Model B has a 40-pin expansion header. Each pin is distinguished by the color.
| Function3| Function3| Function2| Function1| PIN | PIN | Function1| Function2| Function3| Function4|
|-------------|-----------|-------------|-----------|:------|------:|----------|-------------|----------|------------|
| | | | 3V3| 1 | 2 | +5.0V| | | |
| |UART3_RX_M0| I2C3_SDA_M0| GPIO1_A0| 3 | 4 | +5.0V| | | |
| |UART3_TX_M0| I2C3_SCL_M0| GPIO1_A1| 5 | 6 | GND| | | |
| | PWM1_M1| I2C2_SCL_M0| GPIO0_B5| 7 | 8 | GPIO0_D1| UART2_TX_M0| | |
| | | | GND| 9 | 10 | GPIO0_D0| UART2_RX_M0| | |
| |UART7_TX_M1| PWM14_M0| GPIO3_C4| 11 | 12 | GPIO3_A3| | | |
| |UART7_RX_M1| PWM15_IR_M0| GPIO3_C5| 13 | 14 | GND| | | |
| | UART0_RX| PWM1_M0| GPIO0_C0| 15 | 16 | GPIO0_B6| I2C2_SDA_M0| PWM2_M1| |
| | | | +3.3V| 17 | 18 | GPIO3_B2| UART4_TX_M1| PWM9_M0| |
| |PWM15_IR_M1| SPI3_MOSI_M1| GPIO4_C3| 19 | 20 | GND| | | |
| UART9_TX_M1| PWM12_M1| SPI3_MISO_M1| GPIO4_C5| 21 | 22 | GPIO0_C1| PWM2_M0| UART0_TX| |
| | PWM14_M1| SPI3_CLK_M1| GPIO4_C2| 23 | 24 | GPIO4_C6| SPI3_CS0_M1| PWM13_M1| UART9_RX_M1|
| | | | GND| 25 | 26 | GPIO4_D1| SPI3_CS1_M1| | |
| | | I2C1_SDA| GPIO0_B4| 27 | 28 | GPIO4_B3| I2C1_SCL| | |
| | | | GPIO2_D7| 29 | 30 | GND| | | |
| | | | GPIO3_A0| 31 | 32 | GPIO3_C2| UART5_TX_M1| | |
| |SPI1_CLK_M1| UART5_RX_M1| GPIO3_C3| 33 | 34 | GND| | | |
| | | | GPIO3_A4| 35 | 36 | GPIO3_A2| | | |
| | | |SARADC_VIN5| 37 | 38 | GPIO3_A6| | | |
| | | | GND| 39 | 40 | GPIO3_A5| | | |
Supports
--------
You can find additional product support in the following channels:
- [Product Info](https://docs.radxa.com/en/rock3/rock3b)
- [Forums](https://forum.radxa.com/c/rock3)
- [Github](https://github.com/radxa)

30
include/arm/radxa_rock_3b.h Normal file
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@@ -0,0 +1,30 @@
/*
* Author: Nascs <nascs@radxa.com>
* Copyright (c) Radxa Limited.
*
* SPDX-License-Identifier: MIT
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "mraa_internal.h"
#define MRAA_RADXA_ROCK_3B_GPIO_COUNT 28
#define MRAA_RADXA_ROCK_3B_I2C_COUNT 3
#define MRAA_RADXA_ROCK_3B_SPI_COUNT 1
#define MRAA_RADXA_ROCK_3B_UART_COUNT 6
#define MRAA_RADXA_ROCK_3B_PWM_COUNT 11
#define MRAA_RADXA_ROCK_3B_AIO_COUNT 1
#define MRAA_RADXA_ROCK_3B_PIN_COUNT 40
#define PLATFORM_NAME_RADXA_ROCK_3B "Radxa ROCK 3 Model B"
mraa_board_t *
mraa_radxa_rock_3b();
#ifdef __cplusplus
}
#endif

1
src/CMakeLists.txt
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@@ -107,6 +107,7 @@ set (mraa_LIB_ARM_SRCS_NOAUTO
${PROJECT_SOURCE_DIR}/src/arm/phyboard.c
${PROJECT_SOURCE_DIR}/src/arm/banana.c
${PROJECT_SOURCE_DIR}/src/arm/de_nano_soc.c
${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_3b.c
${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_3c.c
${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_5a.c
${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_5b.c

6
src/arm/arm.c
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@@ -10,6 +10,7 @@
#include <string.h>
#include "arm/96boards.h"
#include "arm/radxa_rock_3b.h"
#include "arm/radxa_rock_3c.h"
#include "arm/radxa_rock_5a.h"
#include "arm/radxa_rock_5b.h"
@@ -95,6 +96,8 @@ mraa_arm_platform()
platform_type = MRAA_96BOARDS;
else if (mraa_file_contains("/proc/device-tree/model", "Avnet Ultra96 Rev1"))
platform_type = MRAA_96BOARDS;
else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_ROCK_3B))
platform_type = MRAA_RADXA_ROCK_3B;
else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_ROCK_3C))
platform_type = MRAA_RADXA_ROCK_3C;
else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_ROCK_5A))
@@ -132,6 +135,9 @@ mraa_arm_platform()
case MRAA_96BOARDS:
plat = mraa_96boards();
break;
case MRAA_RADXA_ROCK_3B:
plat = mraa_radxa_rock_3b();
break;
case MRAA_RADXA_ROCK_3C:
plat = mraa_radxa_rock_3c();
break;

166
src/arm/radxa_rock_3b.c Normal file
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@@ -0,0 +1,166 @@
/*
* Author: Nascs <nascs@radxa.com>
* Copyright (c) Radxa Limited.
*
* SPDX-License-Identifier: MIT
*/
#include <mraa/common.h>
#include <stdarg.h>
#include <stdlib.h>
#include <string.h>
#include <sys/mman.h>
#include "arm/radxa_rock_3b.h"
#include "common.h"
const char* radxa_rock_3b_serialdev[MRAA_RADXA_ROCK_3B_UART_COUNT] = { "/dev/ttyS0", "/dev/ttyS2", "/dev/ttyS3", "/dev/ttyS5", "/dev/ttyS7", "/dev/ttyS9" };
void
mraa_radxa_rock_3b_pininfo(mraa_board_t* board, int index, int gpio_chip, int gpio_line, mraa_pincapabilities_t pincapabilities_t, char* pin_name)
{
if (index > board->phy_pin_count)
return;
mraa_pininfo_t* pininfo = &board->pins[index];
strncpy(pininfo->name, pin_name, MRAA_PIN_NAME_SIZE);
if(pincapabilities_t.gpio == 1) {
pininfo->gpio.gpio_chip = gpio_chip;
pininfo->gpio.gpio_line = gpio_line;
}
pininfo->capabilities = pincapabilities_t;
pininfo->gpio.mux_total = 0;
}
mraa_board_t*
mraa_radxa_rock_3b()
{
mraa_board_t* b = (mraa_board_t*) calloc(1, sizeof(mraa_board_t));
if (b == NULL) {
return NULL;
}
b->adv_func = (mraa_adv_func_t*) calloc(1, sizeof(mraa_adv_func_t));
if (b->adv_func == NULL) {
free(b);
return NULL;
}
// pin mux for buses are setup by default by kernel so tell mraa to ignore them
b->no_bus_mux = 1;
b->phy_pin_count = MRAA_RADXA_ROCK_3B_PIN_COUNT + 1;
b->platform_name = PLATFORM_NAME_RADXA_ROCK_3B;
b->chardev_capable = 1;
// UART
b->uart_dev_count = MRAA_RADXA_ROCK_3B_UART_COUNT;
b->def_uart_dev = 0;
b->uart_dev[0].index = 0;
b->uart_dev[1].index = 2;
b->uart_dev[2].index = 3;
b->uart_dev[3].index = 5;
b->uart_dev[4].index = 7;
b->uart_dev[5].index = 9;
b->uart_dev[0].device_path = (char*) radxa_rock_3b_serialdev[0];
b->uart_dev[1].device_path = (char*) radxa_rock_3b_serialdev[1];
b->uart_dev[2].device_path = (char*) radxa_rock_3b_serialdev[2];
b->uart_dev[3].device_path = (char*) radxa_rock_3b_serialdev[3];
b->uart_dev[4].device_path = (char*) radxa_rock_3b_serialdev[4];
b->uart_dev[5].device_path = (char*) radxa_rock_3b_serialdev[5];
// I2C
b->i2c_bus_count = MRAA_RADXA_ROCK_3B_I2C_COUNT;
b->def_i2c_bus = 0;
b->i2c_bus[0].bus_id = 1;
b->i2c_bus[1].bus_id = 2;
b->i2c_bus[2].bus_id = 3;
// SPI
b->spi_bus_count = MRAA_RADXA_ROCK_3B_SPI_COUNT;
b->def_spi_bus = 0;
b->spi_bus[0].bus_id = 3;
// PWM
b->pwm_dev_count = MRAA_RADXA_ROCK_3B_PWM_COUNT;
b->pwm_default_period = 500;
b->pwm_max_period = 2147483;
b->pwm_min_period = 1;
b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t) * b->phy_pin_count);
if (b->pins == NULL) {
free(b->adv_func);
free(b);
return NULL;
}
b->pins[15].pwm.parent_id = 1; // pwm1-m0
b->pins[15].pwm.mux_total = 0;
b->pins[7].pwm.parent_id = 1; // pwm1-m1
b->pins[7].pwm.mux_total = 0;
b->pins[22].pwm.parent_id = 2; // pwm2-m0
b->pins[22].pwm.mux_total = 0;
b->pins[16].pwm.parent_id = 2; // pwm2-m1
b->pins[16].pwm.mux_total = 0;
b->pins[18].pwm.parent_id = 9; // pwm9-m0
b->pins[18].pwm.mux_total = 0;
b->pins[21].pwm.parent_id = 12; // pwm12-m1
b->pins[21].pwm.mux_total = 0;
b->pins[24].pwm.parent_id = 13; // pwm13-m1
b->pins[24].pwm.mux_total = 0;
b->pins[11].pwm.parent_id = 14; // pwm14-m0
b->pins[11].pwm.mux_total = 0;
b->pins[23].pwm.parent_id = 14; // pwm14-m1
b->pins[23].pwm.mux_total = 0;
b->pins[13].pwm.parent_id = 15; // pwm15-m0
b->pins[13].pwm.mux_total = 0;
b->pins[19].pwm.parent_id = 15; // pwm15-m1
b->pins[19].pwm.mux_total = 0;
mraa_radxa_rock_3b_pininfo(b, 0, -1, -1, (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, "INVALID");
mraa_radxa_rock_3b_pininfo(b, 1, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3");
mraa_radxa_rock_3b_pininfo(b, 2, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "5V");
mraa_radxa_rock_3b_pininfo(b, 3, 1, 0, (mraa_pincapabilities_t){1,0,0,0, 0,1,0,1}, "GPIO1_A0"); // GPIO1_A0 was used by audiopwm, function GPIO cannot be enabled
mraa_radxa_rock_3b_pininfo(b, 4, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "5V");
mraa_radxa_rock_3b_pininfo(b, 5, 1, 1, (mraa_pincapabilities_t){1,0,0,0, 0,1,0,1}, "GPIO1_A1"); // GPIO1_A1 was used by audiopwm, function GPIO cannot be enabled
mraa_radxa_rock_3b_pininfo(b, 6, -1, -1, (mraa_pincapabilities_t){1,0,0,0, 0,0,0,0}, "GND");
mraa_radxa_rock_3b_pininfo(b, 7, 0, 13, (mraa_pincapabilities_t){1,0,1,0,0,1,0,0}, "GPIO0_B5"); // hardware pull up, function GPIO cannot be enabled
mraa_radxa_rock_3b_pininfo(b, 8, 0, 25, (mraa_pincapabilities_t){1,0,0,0,0,0,0,1}, "GPIO0_D1"); // GPIO0_D1 was used by fiq_debugger, function GPIO cannot be enabled
mraa_radxa_rock_3b_pininfo(b, 9, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_3b_pininfo(b, 10, 0, 24, (mraa_pincapabilities_t){1,0,0,0,0,0,0,1}, "GPIO0_D0"); // GPIO0_D0 was used by fiq_debugger, function GPIO cannot be enabled
mraa_radxa_rock_3b_pininfo(b, 11, 3, 20, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO3_C4");
mraa_radxa_rock_3b_pininfo(b, 12, 3, 3, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_A3");
mraa_radxa_rock_3b_pininfo(b, 13, 3, 21, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO3_C5");
mraa_radxa_rock_3b_pininfo(b, 14, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_3b_pininfo(b, 15, 0, 16, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO0_C0");
mraa_radxa_rock_3b_pininfo(b, 16, 0, 14, (mraa_pincapabilities_t){1,0,1,0,0,1,0,0}, "GPIO0_B6"); // Hardware pull up, function GPIO cannot be enabled
mraa_radxa_rock_3b_pininfo(b, 17, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3");
mraa_radxa_rock_3b_pininfo(b, 18, 3, 10, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO3_B2");
mraa_radxa_rock_3b_pininfo(b, 19, 4, 19, (mraa_pincapabilities_t){1,1,1,0,1,0,0,0}, "GPIO4_C3");
mraa_radxa_rock_3b_pininfo(b, 20, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_3b_pininfo(b, 21, 4, 21, (mraa_pincapabilities_t){1,1,1,0,1,0,0,1}, "GPIO4_C5");
mraa_radxa_rock_3b_pininfo(b, 22, 0, 17, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO0_C1");
mraa_radxa_rock_3b_pininfo(b, 23, 4, 18, (mraa_pincapabilities_t){1,1,1,0,1,0,0,0}, "GPIO4_C2");
mraa_radxa_rock_3b_pininfo(b, 24, 4, 22, (mraa_pincapabilities_t){1,1,1,0,1,0,0,1}, "GPIO4_C6");
mraa_radxa_rock_3b_pininfo(b, 25, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_3b_pininfo(b, 26, 4, 25, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO4_D1");
mraa_radxa_rock_3b_pininfo(b, 27, 0, 12, (mraa_pincapabilities_t){1,1,0,0,0,1,0,0}, "GPIO0_B4");
mraa_radxa_rock_3b_pininfo(b, 28, 0, 11, (mraa_pincapabilities_t){1,1,0,0,0,1,0,0}, "GPIO0_B3");
mraa_radxa_rock_3b_pininfo(b, 29, 2, 31, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO2_D7");
mraa_radxa_rock_3b_pininfo(b, 30, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_3b_pininfo(b, 31, 3, 0, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_A0");
mraa_radxa_rock_3b_pininfo(b, 32, 3, 18, (mraa_pincapabilities_t){1,1,0,0,0,0,0,1}, "GPIO3_C2");
mraa_radxa_rock_3b_pininfo(b, 33, 3, 19, (mraa_pincapabilities_t){1,1,0,0,1,0,0,1}, "GPIO3_C3");
mraa_radxa_rock_3b_pininfo(b, 34, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_3b_pininfo(b, 35, 3, 4, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_A4");
mraa_radxa_rock_3b_pininfo(b, 36, 3, 2, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_A2");
mraa_radxa_rock_3b_pininfo(b, 37, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,1,0}, "SARADC_VIN5");
mraa_radxa_rock_3b_pininfo(b, 38, 3, 6, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_A6");
mraa_radxa_rock_3b_pininfo(b, 39, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_3b_pininfo(b, 40, 3, 5, (mraa_pincapabilities_t){1,1,0,0,0,0,0,0}, "GPIO3_A5");
return b;
}