d954599045
UP Xtreme is based on the Intel(R) Core(TM) i3/i5/i7 Whiskey Lake SoCs. The UP Xtreme presents one Raspberry Pi compatible HAT connector. This implementaion supports i2c, spi, uart, adc and gpio through the 40pin HAT connector. Gpio chardev capabilities have been disabled in this implementation. When gpio chardev capabilities are enabled an input becomes unreadable after an isr has been registered to the pin. See here for details: https://github.com/intel-iot-devkit/mraa/issues/937 Tested on UP Xtreme, with UP Board Linux kernel 5.0.0 Features tested: gpio, gpio interrupts, i2c, spi, adc and uart. Signed-off-by: Michael Campion <michael.campion@emutex.com>
86 lines
4.7 KiB
Markdown
86 lines
4.7 KiB
Markdown
UP Xtreme Board {#up_xtreme}
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================================
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UP Xtreme is based on the Intel® Core™ i3/i5/i7 Whiskey Lake SoCs.
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For the full specification please refer to the main specification page here:
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https://up-board.org/wp-content/uploads/up-xtreme/Datasheet-UP-xtreme.pdf
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Interface notes
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-----------------------
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The UP Xtreme present one Raspberry Pi compatible HAT connector and a 100 pin exHAT connector. Currently this implementation only support the interfaces through the HAT connector.
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**I2C**
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- 2 channels
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- Support: standard-mode (100kHz), fast-mode (400kHz), Fast-mode plus (1MHz), High-speed mode (3.4MHz)
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- Bus frequency can be selected in BIOS settings
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- The default i2c channel is the one connected to the pin 3,5 of the hat
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- On some OSes the i2c-dev kernel module may need to be loaded manually to export the i2c device nodes
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**SPI**
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- Bus frequencies up to 10MHz are supported
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- 2 chip-selects
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- To enable SPI device nodes the ACPI tables need to be overwritten as explained [here](https://wiki.up-community.org/Pinout_UP2#SPI_Ports)
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**UART**
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- 1 high-speed UART is available
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- Supporting baud rates up to 3686400 baud
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- Hardware flow-control signals are available on pins 11/36 (RTS/CTS)
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Please note that a kernel with UP board support is required to enable the I/O
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interfaces above.
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Refer to http://www.up-community.org for more information.
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Pin Mapping
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--------------------
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The GPIO numbering in the following pin mapping is based on the Raspberry Pi
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model 2 and B+ numbering scheme.
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NOTE: the i2c device numbering depend on various factor and cannot be trusted:
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the right way of determining i2c (and other devices) numbering is through PCI
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physical device names. See the source code in src/x86/up_xtreme.c for details.
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| MRAA no. | Function | Rpi GPIO | Sysfs GPIO | mraa device |
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|----------|--------------|------------|------------|-----------------|
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| 1 | 3V3 VCC | | | |
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| 2 | 5V VCC | | | |
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| 3 | I2C_SDA | 2 | 368 | I2C0 |
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| 4 | 5V VCC | | | |
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| 5 | I2C_SCL | 3 | 369 | I2C0 |
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| 6 | GND | | | |
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| 7 | GPIO(4) | 4 | 296 | |
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| 8 | UART_TX | 14 | 469 | UART0 |
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| 9 | GND | | | |
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| 10 | UART_RX | 15 | 468 | UART0 |
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| 11 | UART_RTS | 17 | 470 | UART0 |
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| 12 | I2S_CLK | 18 | 360 | |
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| 13 | GPIO(27) | 27 | 268 | |
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| 14 | GND | | | |
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| 15 | GPIO(22) | 22 | 270 | |
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| 16 | GPIO(23) | 23 | 264 | |
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| 17 | 3V3 VCC | | | |
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| 18 | GPIO(24) | 24 | 265 | |
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| 19 | SPI0_MOSI | 10 | 308 | SPI0 |
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| 20 | GND | | | |
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| 21 | SPI0_MISO | 9 | 307 | SPI0 |
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| 22 | GPIO(25) | 25 | 266 | |
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| 23 | SPI0_SCL | 11 | 306 | SPI0 |
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| 24 | SPI0_CS0 | 8 | 305 | SPI0 |
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| 25 | GND | | | |
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| 26 | SPI0_CS1 | 7 | 311 | SPI0 |
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| 27 | ID_SD | 0 | 366 | I2C1 |
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| 28 | ID_SC | 1 | 367 | I2C1 |
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| 29 | GPIO(5) | 5 | 317 | |
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| 30 | GND | | | |
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| 31 | GPIO(6) | 6 | 318 | |
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| 32 | GPIO(12) | 12 | 298 | |
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| 33 | GPIO(13) | 13 | 299 | |
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| 34 | GND | | | |
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| 35 | I2S_FRM | 19 | 261 | |
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| 36 | UART_CTS | 16 | 471 | UART0 |
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| 37 | GPIO(26) | 26 | 267 | |
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| 38 | I2S_DIN | 20 | 363 | |
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| 39 | GND | | | |
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| 40 | I2S_DOUT | 21 | 362 | |
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