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platform: add Radxa ROCK 5A platform support

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Signed-off-by: Nascs <nascs@radxa.com>
This commit is contained in:
nascs
2023-07-25 10:26:07 +00:00
committed by Tom Ingleby
parent 200c0a0491
commit 7a45f17f79
8 changed files with 336 additions and 0 deletions
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1
README.md
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@@ -45,6 +45,7 @@ ARM
* [phyBOARD-Wega](../master/docs/phyboard-wega.md)
* [96Boards](../master/docs/96boards.md)
* [ADLINK IPi-SMARC ARM](../master/docs/adlink_ipi_arm.md)
* [Radxa ROCK 5A](../mraa//docs/radxa_rock_5a.md)
* [Rock Pi 4](../master/docs/rockpi4.md)
MIPS

35
api/mraa/types.h
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@@ -71,6 +71,7 @@ typedef enum {
MRAA_SIEMENS_IOT2050 = 26, /**< Siemens IOT2050 board */
MRAA_RADXA_ROCK_3C = 27, /**< Radxa ROCK 3 Model C */
MRAA_VISIONFIVE = 28, /**< StarFive VisionFive board */
MRAA_RADXA_ROCK_5A = 29, /**< Radxa ROCK 5 Model A */
// USB platform extenders start at 256
MRAA_FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */
@@ -178,6 +179,40 @@ typedef enum {
MRAA_INTEL_EDISON_GP81 = 55
} mraa_intel_edison_t;
/**
* Radxa ROCK 5 Model A GPIO numbering enum
*/
typedef enum {
MRAA_RADXA_ROCK_5A_PIN3 = 3,
MRAA_RADXA_ROCK_5A_PIN5 = 5,
MRAA_RADXA_ROCK_5A_PIN7 = 7,
MRAA_RADXA_ROCK_5A_PIN8 = 8,
MRAA_RADXA_ROCK_5A_PIN10 = 10,
MRAA_RADXA_ROCK_5A_PIN11 = 11,
MRAA_RADXA_ROCK_5A_PIN12 = 12,
MRAA_RADXA_ROCK_5A_PIN13 = 13,
MRAA_RADXA_ROCK_5A_PIN15 = 15,
MRAA_RADXA_ROCK_5A_PIN16 = 16,
MRAA_RADXA_ROCK_5A_PIN18 = 18,
MRAA_RADXA_ROCK_5A_PIN19 = 19,
MRAA_RADXA_ROCK_5A_PIN21 = 21,
MRAA_RADXA_ROCK_5A_PIN22 = 22,
MRAA_RADXA_ROCK_5A_PIN23 = 23,
MRAA_RADXA_ROCK_5A_PIN24 = 24,
MRAA_RADXA_ROCK_5A_PIN26 = 26,
MRAA_RADXA_ROCK_5A_PIN27 = 27,
MRAA_RADXA_ROCK_5A_PIN28 = 28,
MRAA_RADXA_ROCK_5A_PIN29 = 29,
MRAA_RADXA_ROCK_5A_PIN31 = 31,
MRAA_RADXA_ROCK_5A_PIN32 = 32,
MRAA_RADXA_ROCK_5A_PIN33 = 33,
MRAA_RADXA_ROCK_5A_PIN35 = 35,
MRAA_RADXA_ROCK_5A_PIN36 = 36,
MRAA_RADXA_ROCK_5A_PIN37 = 37,
MRAA_RADXA_ROCK_5A_PIN38 = 38,
MRAA_RADXA_ROCK_5A_PIN40 = 40
} mraa_radxa_rock_5a_wiring_t;
/**
* Radxa ROCK 3 Model C GPIO numbering enum
*/

35
api/mraa/types.hpp
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@@ -65,6 +65,7 @@ typedef enum {
SIEMENS_IOT2050 = 26, /**< Siemens IOT2050 board */
RADXA_ROCK_3C = 27, /**< Radxa ROCK 3 Model C */
VISIONFIVE = 28, /**< StarFive VisionFive board */
RADXA_ROCK_5A = 29, /**< Radxa ROCK 5 Model A */
FTDI_FT4222 = 256, /**< FTDI FT4222 USB to i2c bridge */
@@ -169,6 +170,40 @@ typedef enum {
INTEL_EDISON_GP81 = 55
} IntelEdison;
/**
* Radxa ROCK 5 Model A GPIO numbering enum
*/
typedef enum {
RADXA_ROCK_5A_PIN3 = 3,
RADXA_ROCK_5A_PIN5 = 5,
RADXA_ROCK_5A_PIN7 = 7,
RADXA_ROCK_5A_PIN8 = 8,
RADXA_ROCK_5A_PIN10 = 10,
RADXA_ROCK_5A_PIN11 = 11,
RADXA_ROCK_5A_PIN12 = 12,
RADXA_ROCK_5A_PIN13 = 13,
RADXA_ROCK_5A_PIN15 = 15,
RADXA_ROCK_5A_PIN16 = 16,
RADXA_ROCK_5A_PIN18 = 18,
RADXA_ROCK_5A_PIN19 = 19,
RADXA_ROCK_5A_PIN21 = 21,
RADXA_ROCK_5A_PIN22 = 22,
RADXA_ROCK_5A_PIN23 = 23,
RADXA_ROCK_5A_PIN24 = 24,
RADXA_ROCK_5A_PIN26 = 26,
RADXA_ROCK_5A_PIN27 = 27,
RADXA_ROCK_5A_PIN28 = 28,
RADXA_ROCK_5A_PIN29 = 29,
RADXA_ROCK_5A_PIN31 = 31,
RADXA_ROCK_5A_PIN32 = 32,
RADXA_ROCK_5A_PIN33 = 33,
RADXA_ROCK_5A_PIN35 = 35,
RADXA_ROCK_5A_PIN36 = 36,
RADXA_ROCK_5A_PIN37 = 37,
RADXA_ROCK_5A_PIN38 = 38,
RADXA_ROCK_5A_PIN40 = 40
} RadxaRock5AWiring;
/**
* Radxa ROCK 3 Model C GPIO numbering enum
*/

47
docs/radxa_rock_5a.md Normal file
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@@ -0,0 +1,47 @@
Radxa ROCK 5 Model A {#_Radxa}
====================
Radxa ROCK 5A is a Rockchip RK3588s based SBC(Single Board Computer) by Radxa. It can run android or some Linux distributions. Radxa ROCK 5A features a eight core ARM processor, 64bit dual channel 3200Mb/s LPDDR4, up to 8Kp60 HDMI, MIPI DSI, MIPI CSI, 3.5mm jack with mic, 802.11 ac WIFI, Bluetooth 5.0, USB Port, GbE LAN, 40-pin color expansion header, RTC. Also, Radxa ROCK 5A supports USB PD and QC powering.
Interface notes
---------------
- UART2 is enabled as the default console.
- All UART ports support baud up to 1500000.
Pin Mapping
-----------
Radxa ROCK 5A has a 40-pin expansion header. Each pin is distinguished by color.
|Function4 |Function3 |Function2 |Function1 | | PIN | PIN | Function1| Function2| Function3|
|------------|------------|------------|-----------|:------|------:|---------|------------|-----------|------------|
| | | |+3.3V | 1 | 2 | +5.0V| | | |
| |PWM15_IR_M3 |I2C8_SDA_M2 |GPIO1_D7 | 3 | 4 | +5.0V| UART2_TX_M0|I2C1_SCL_M0| |
| |PWM14_M2 |I2C8_SCL_M2 |GPIO1_D6 | 5 | 6 | GND| UART2_RX_M0|I2C1_SDA_M0| |
| |UART4_TX_M2 |SPI0_CLK_M2 |GPIO1_B3 | 7 | 8 | GPIO0_B5|SPI0_MOSI_M1| | |
| | | |GND | 9 | 10 | GPIO0_B6| | | |
| |PWM15_IR_M1 |I2C7_SDA_M3 |GPIO4_B3 | 11 | 12 | GPIO4_A1| | | |
|PWM14_M1 |SPI0_CS0_M1 |I2C7_SCL_M3 |GPIO4_B2 | 13 | 14 | GND| | | |
| |PWM11_IR_M1 |UART9_TX_M1 |GPIO4_B4 | 15 | 16 | GPIO1_A5|SPI2_MOSI_M0| | |
| | | |+3.3 | 17 | 18 | GPIO1_B0| SPI2_CS1_M0| | |
|UART6_TX_M1 |SPI4_MOSI_M2|I2C2_SCL_M4 |GPIO1_A1 | 19 | 20 | GND| | | |
|UART6_RX_M1 |SPI4_MISO_M2|I2C2_SDA_M4 |GPIO1_A0 | 21 | 22 | GPIO1_B5| SPI0_CS1_M2|UART7_TX_M2| |
|PWM0_M2 |SPI4_CLK_M2 |I2C4_SDA_M3 |GPIO1_A2 | 23 | 24 | GPIO1_A3| I2C4_SCL_M3|SPI4_CS0_M2| PWM1_M2|
| | | | GND | 25 | 26 | GPIO1_A4|SPI2_MISO_M0| | |
|SPI0_MISO_M0|I2C6_SDA_M0 |PWM6_M0 |GPIO0_C7 | 27 | 28 | GPIO0_D0| PWM7_IR_M0|I2C6_SCL_M0|SPI3_MISO_M2|
| |UART4_RX_M2 |SPI0_MOSI_M |GPIO1_B2 | 29 | 30 | GND| | | |
| | |SPI0_MISO_M2|GPIO1_B1 | 31 | 32 | GPIO4_B0| I2C6_SDA_M3|SPI2_CS1_M1| UART8_TX_M0|
| |UART7_RX_M2 |SPI0_CS0_M2 |GPIO1_B4 | 33 | 34 | GND| | | |
| | |SPI0_MISO_M1|GPIO4_A0 | 35 | 36 | GPIO4_A2| SPI0_CLK_M1| | |
| | | |SARADC_VIN2| 37 | 38 | GPIO4_A5| I2C3_SDA_M2|UART3_TX_M2| |
| | | |GND | 39 | 40 | GPIO4_B1| I2C6_SCL_M3|SPI0_CS1_M1| UART8_RX_M0|
Resources
---------
You can find additional product support in the following channels:
- [Product Info](https://docs.radxa.com/en/rock5/rock5a)
- [Forums](https://forum.radxa.com/c/rock5)
- [Github](https://github.com/radxa)

30
include/arm/radxa_rock_5a.h Normal file
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@@ -0,0 +1,30 @@
/*
* Author: Nascs <nascs@radxa.com>
* Copyright (c) Radxa Limited.
*
* SPDX-License-Identifier: MIT
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "mraa_internal.h"
#define MRAA_RADXA_ROCK_5A_GPIO_COUNT 27
#define MRAA_RADXA_ROCK_5A_I2C_COUNT 5
#define MRAA_RADXA_ROCK_5A_SPI_COUNT 2
#define MRAA_RADXA_ROCK_5A_UART_COUNT 5
#define MRAA_RADXA_ROCK_5A_PWM_COUNT 9
#define MRAA_RADXA_ROCK_5A_AIO_COUNT 1
#define MRAA_RADXA_ROCK_5A_PIN_COUNT 40
#define PLATFORM_NAME_RADXA_ROCK_5A "Radxa ROCK 5A"
mraa_board_t *
mraa_radxa_rock_5a();
#ifdef __cplusplus
}
#endif

1
src/CMakeLists.txt
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@@ -108,6 +108,7 @@ set (mraa_LIB_ARM_SRCS_NOAUTO
${PROJECT_SOURCE_DIR}/src/arm/banana.c
${PROJECT_SOURCE_DIR}/src/arm/de_nano_soc.c
${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_3c.c
${PROJECT_SOURCE_DIR}/src/arm/radxa_rock_5a.c
${PROJECT_SOURCE_DIR}/src/arm/rockpi4.c
${PROJECT_SOURCE_DIR}/src/arm/adlink_ipi.c
${PROJECT_SOURCE_DIR}/src/arm/siemens/iot2050.c

6
src/arm/arm.c
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@@ -11,6 +11,7 @@
#include "arm/96boards.h"
#include "arm/radxa_rock_3c.h"
#include "arm/radxa_rock_5a.h"
#include "arm/rockpi4.h"
#include "arm/de_nano_soc.h"
#include "arm/banana.h"
@@ -94,6 +95,8 @@ mraa_arm_platform()
platform_type = MRAA_96BOARDS;
else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_ROCK_3C))
platform_type = MRAA_RADXA_ROCK_3C;
else if (mraa_file_contains("/proc/device-tree/model", PLATFORM_NAME_RADXA_ROCK_5A))
platform_type = MRAA_RADXA_ROCK_5A;
else if (mraa_file_contains("/proc/device-tree/model", "ROCK Pi 4") ||
mraa_file_contains("/proc/device-tree/model", "ROCK PI 4") ||
mraa_file_contains("/proc/device-tree/model", "ROCK 4")
@@ -126,6 +129,9 @@ mraa_arm_platform()
case MRAA_RADXA_ROCK_3C:
plat = mraa_radxa_rock_3c();
break;
case MRAA_RADXA_ROCK_5A:
plat = mraa_radxa_rock_5a();
break;
case MRAA_ROCKPI4:
plat = mraa_rockpi4();
break;

181
src/arm/radxa_rock_5a.c Normal file
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@@ -0,0 +1,181 @@
/*
* Author: Nascs <nascs@radxa.com>
* Copyright (c) Radxa Limited.
*
* SPDX-License-Identifier: MIT
*/
#include <mraa/common.h>
#include <stdarg.h>
#include <stdlib.h>
#include <string.h>
#include <sys/mman.h>
#include "arm/radxa_rock_5a.h"
#include "common.h"
#define DT_BASE "/proc/device-tree"
const char* radxa_rock_5a_serialdev[MRAA_RADXA_ROCK_5A_UART_COUNT] = { "/dev/ttyS2", "/dev/ttyS4", "/dev/ttyS6", "/dev/ttyS7", "/dev/ttyS8"};
void
mraa_radxa_rock_5a_pininfo(mraa_board_t* board, int index, int gpio_chip, int gpio_line, mraa_pincapabilities_t pincapabilities_t, char* pin_name)
{
if (index > board->phy_pin_count)
return;
mraa_pininfo_t* pininfo = &board->pins[index];
strncpy(pininfo->name, pin_name, MRAA_PIN_NAME_SIZE);
if(pincapabilities_t.gpio == 1) {
pininfo->gpio.gpio_chip = gpio_chip;
pininfo->gpio.gpio_line = gpio_line;
}
pininfo->capabilities = pincapabilities_t;
pininfo->gpio.mux_total = 0;
}
mraa_board_t*
mraa_radxa_rock_5a()
{
mraa_board_t* b = (mraa_board_t*) calloc(1, sizeof(mraa_board_t));
if (b == NULL) {
return NULL;
}
b->adv_func = (mraa_adv_func_t*) calloc(1, sizeof(mraa_adv_func_t));
if (b->adv_func == NULL) {
free(b);
return NULL;
}
// pin mux for buses are setup by default by kernel so tell mraa to ignore them
b->no_bus_mux = 1;
b->phy_pin_count = MRAA_RADXA_ROCK_5A_PIN_COUNT + 1;
// UART
b->uart_dev_count = MRAA_RADXA_ROCK_5A_UART_COUNT;
b->platform_name = PLATFORM_NAME_RADXA_ROCK_5A;
b->def_uart_dev = 0;
b->uart_dev[0].index = 2;
b->uart_dev[1].index = 4;
b->uart_dev[2].index = 6;
b->uart_dev[3].index = 7;
b->uart_dev[4].index = 8;
b->uart_dev[0].device_path = (char*) radxa_rock_5a_serialdev[0];
b->uart_dev[1].device_path = (char*) radxa_rock_5a_serialdev[1];
b->uart_dev[2].device_path = (char*) radxa_rock_5a_serialdev[2];
b->uart_dev[3].device_path = (char*) radxa_rock_5a_serialdev[3];
b->uart_dev[4].device_path = (char*) radxa_rock_5a_serialdev[4];
// I2C
b->i2c_bus_count = MRAA_RADXA_ROCK_5A_I2C_COUNT;
b->def_i2c_bus = 0;
b->i2c_bus[0].bus_id = 1;
b->i2c_bus[1].bus_id = 2;
b->i2c_bus[2].bus_id = 4;
b->i2c_bus[3].bus_id = 6;
b->i2c_bus[4].bus_id = 8;
// SPI
b->spi_bus_count = MRAA_RADXA_ROCK_5A_SPI_COUNT;
b->def_spi_bus = 0;
b->spi_bus[0].bus_id = 0;
b->spi_bus[1].bus_id = 4;
// PWM
b->pwm_dev_count = MRAA_RADXA_ROCK_5A_PWM_COUNT;
b->pwm_default_period = 500;
b->pwm_max_period = 2147483;
b->pwm_min_period = 1;
b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t) * b->phy_pin_count);
if (b->pins == NULL) {
free(b->adv_func);
free(b);
return NULL;
}
b->pins[3].pwm.parent_id = 15; // PWM15_M3
b->pins[3].pwm.mux_total = 0;
b->pins[3].pwm.pinmap = 0;
b->pins[5].pwm.parent_id = 14; // PWM14_M2
b->pins[5].pwm.mux_total = 0;
b->pins[5].pwm.pinmap = 0;
b->pins[11].pwm.parent_id = 15; // PWM15_M1
b->pins[11].pwm.mux_total = 0;
b->pins[11].pwm.pinmap = 0;
b->pins[13].pwm.parent_id = 14; // PWM14_M1
b->pins[13].pwm.mux_total = 0;
b->pins[13].pwm.pinmap = 0;
b->pins[15].pwm.parent_id = 11; // PWM11_M1
b->pins[15].pwm.mux_total = 0;
b->pins[15].pwm.pinmap = 0;
b->pins[23].pwm.parent_id = 0; // PWM0_M2
b->pins[23].pwm.mux_total = 0;
b->pins[23].pwm.pinmap = 0;
b->pins[27].pwm.parent_id = 6; // PWM6_M0
b->pins[27].pwm.mux_total = 0;
b->pins[27].pwm.pinmap = 0;
b->pins[28].pwm.parent_id = 7; // PWM7_M0
b->pins[28].pwm.mux_total = 0;
b->pins[28].pwm.pinmap = 0;
b->pins[28].pwm.parent_id = 1; // PWM1_M2
b->pins[28].pwm.mux_total = 0;
b->pins[28].pwm.pinmap = 0;
// AIO
b->aio_count = MRAA_RADXA_ROCK_5A_AIO_COUNT;
b->adc_raw = 10;
b->adc_supported = 10;
b->aio_dev[0].pin = 37;
b->aio_non_seq = 1;
b->chardev_capable = 1;
// Hardware X1.2
mraa_radxa_rock_5a_pininfo(b, 0, -1, -1, (mraa_pincapabilities_t){0,0,0,0,0,0,0,0}, "INVALID");
mraa_radxa_rock_5a_pininfo(b, 1, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3");
mraa_radxa_rock_5a_pininfo(b, 2, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "5V");
mraa_radxa_rock_5a_pininfo(b, 3, 1, 31, (mraa_pincapabilities_t){1,1,1,0,0,1,0,0}, "GPIO1_D7");
mraa_radxa_rock_5a_pininfo(b, 4, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "5V");
mraa_radxa_rock_5a_pininfo(b, 5, 1, 30, (mraa_pincapabilities_t){1,1,1,0,0,1,0,0}, "GPIO1_D6");
mraa_radxa_rock_5a_pininfo(b, 6, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_5a_pininfo(b, 7, 1, 11, (mraa_pincapabilities_t){1,1,0,0,1,0,0,1}, "GPIO1_B3");
mraa_radxa_rock_5a_pininfo(b, 8, 0, 13, (mraa_pincapabilities_t){1,0,0,0,0,1,0,1}, "GPIO0_B5"); // Used by fiq_debugger
mraa_radxa_rock_5a_pininfo(b, 9, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_5a_pininfo(b, 10, 0, 14, (mraa_pincapabilities_t){1,0,0,0,0,1,0,1}, "GPIO0_B6"); // Used by fiq_debugger
mraa_radxa_rock_5a_pininfo(b, 11, 4, 11, (mraa_pincapabilities_t){1,1,1,0,0,0,0,0}, "GPIO4_B3"); // I2C-M0 is used by on-board devices
mraa_radxa_rock_5a_pininfo(b, 12, 4, 1, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO4_A1");
mraa_radxa_rock_5a_pininfo(b, 13, 4, 10, (mraa_pincapabilities_t){1,1,1,0,1,0,0,0}, "GPIO4_B2"); // I2C-M0 is used by on-board devices
mraa_radxa_rock_5a_pininfo(b, 14, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_5a_pininfo(b, 15, 4, 12, (mraa_pincapabilities_t){1,1,1,0,0,0,0,1}, "GPIO4_B4");
mraa_radxa_rock_5a_pininfo(b, 16, 1, 5, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO1_A5");
mraa_radxa_rock_5a_pininfo(b, 17, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "3V3");
mraa_radxa_rock_5a_pininfo(b, 18, 1, 8, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO1_B0");
mraa_radxa_rock_5a_pininfo(b, 19, 1, 1, (mraa_pincapabilities_t){1,1,0,0,1,1,0,1}, "GPIO1_A1");
mraa_radxa_rock_5a_pininfo(b, 20, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_5a_pininfo(b, 21, 1, 0, (mraa_pincapabilities_t){1,1,0,0,1,1,0,1}, "GPIO1_A0");
mraa_radxa_rock_5a_pininfo(b, 22, 1, 13, (mraa_pincapabilities_t){1,1,0,0,1,0,0,1}, "GPIO1_B5");
mraa_radxa_rock_5a_pininfo(b, 23, 1, 2, (mraa_pincapabilities_t){1,1,1,0,1,1,0,0}, "GPIO1_A2");
mraa_radxa_rock_5a_pininfo(b, 24, 1, 3, (mraa_pincapabilities_t){1,1,1,0,1,1,0,0}, "GPIO1_A3");
mraa_radxa_rock_5a_pininfo(b, 25, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_5a_pininfo(b, 26, 1, 4, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO1_A4");
mraa_radxa_rock_5a_pininfo(b, 27, 0, 23, (mraa_pincapabilities_t){1,1,1,0,1,1,0,0}, "GPIO0_C7");
mraa_radxa_rock_5a_pininfo(b, 28, 0, 24, (mraa_pincapabilities_t){1,1,1,0,1,1,0,0}, "GPIO0_D0");
mraa_radxa_rock_5a_pininfo(b, 29, 1, 10, (mraa_pincapabilities_t){1,1,0,0,1,0,0,1}, "GPIO1_B2");
mraa_radxa_rock_5a_pininfo(b, 30, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_5a_pininfo(b, 31, 1, 9, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO1_B1");
mraa_radxa_rock_5a_pininfo(b, 32, 4, 8, (mraa_pincapabilities_t){1,1,0,0,1,1,0,1}, "GPIO4_B0");
mraa_radxa_rock_5a_pininfo(b, 33, 1, 12, (mraa_pincapabilities_t){1,1,0,0,1,0,0,1}, "GPIO1_B4");
mraa_radxa_rock_5a_pininfo(b, 34, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_5a_pininfo(b, 35, 4, 0, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO4_A0");
mraa_radxa_rock_5a_pininfo(b, 36, 4, 2, (mraa_pincapabilities_t){1,1,0,0,1,0,0,0}, "GPIO4_A2");
mraa_radxa_rock_5a_pininfo(b, 37, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,1,0}, "SARADC_VIN2");
mraa_radxa_rock_5a_pininfo(b, 38, 4, 5, (mraa_pincapabilities_t){1,1,0,0,0,1,0,1}, "GPIO4_A5");
mraa_radxa_rock_5a_pininfo(b, 39, -1, -1, (mraa_pincapabilities_t){1,0,0,0,0,0,0,0}, "GND");
mraa_radxa_rock_5a_pininfo(b, 40, 4, 9, (mraa_pincapabilities_t){1,1,0,0,1,1,0,1}, "GPIO4_B1");
return b;
}