Add onboard LED support for Dragonboard410c. There are 4 user LEDs and
two LEDs for BT and WLAN.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
On Dragonboard410c, configure SPI0_CS pin as GPIO for enabling the
user to control it without adding chip select property in Devicetree.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
This commit adds Ultra96, one of the Consumer Edition boards of the
96Boards family.
Ultra96 is an Arm-based, Xilinx Zynq UltraScale+ MPSoC development board.
This board runs petalinux distribution on the ARM core and integrates
Xilinx programmable logic (PL) UltraScale architecture in a single fabric.
This board supports standard peripherals defined by 96Boards CE
Specification. Since it ships with >4.8 kernel, only chardev mapping
is supported for accessing GPIO.
More information about this board can be found in 96Boards product
page: https://www.96boards.org/product/ultra96/
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
This commit cleans up the 96boards board support by sorting the boards
in alphabetical manner and also executing clang-format for 96boards.c
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Add support for Hikey960 board from HiSilicon based on their Kirin960 SoC.
Peripherals supported:
1. GPIO
2. UART
3. I2C
For GPIO only Chardev interface has been added since this board only supports
>=4.15 kernel and using legacy sysfs interface is highly discouraged.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: malikabhi05 <abhishek.malik@intel.com>
Move the chardev enablement inside the platform check.
Some boards might not have the chardev mapping yet.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: malikabhi05 <abhishek.malik@intel.com>
As of now both Dragonboard410c and Hikey boards run latest LTS kernel.
Hence, adding chardev support for those.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: malikabhi05 <abhishek.malik@intel.com>
The Pi doesn't have userspace level PWM support, but you can mmap the
raw registers and configure it that way, which is what this patch is
doing. Tested with Raspberry Pi 3 B. I am able to set the duty cycle,
change the frequency, and set the pulse width. Signals verified with
logic analyzer. Note that the only accessible pwm is on GPIO18, which is
also used by the audio subsystem.
Signed-off-by: Nick Crast <nicholas.crast@anaren.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
There were unused variables, incorrect pointer operations
and plan broken string comparison.
Now there's only one - for unused uart3_enabled in beaglebone.c,
but we want to keep it for declaration consistency.
Also fixes#757.
Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
Beaglebone AIO pins seem to be a little different than most boards, so
this is my attempt to work with that without impacting other boards. I
added a new flag in mraa_board_t to indicate whether or not the aio pins
are sequential. One the beaglebone, they are not. To go along with this,
I added a new device mraa_aio_dev_t, that will map each aio to a
physical pin.
In the main aio logic, if aio_non_seq is true for the board, the manual
mapping is used, otherwise the old mathematical mapping is used.
Signed-off-by: Nick Crast <nrcrast@gmail.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
Made the pin declarations a little nicer to look at. Found a bug with
the I2C. The higher layers were passing the bus ID itself, not the index
of the device in the i2c_bus array.
Signed-off-by: Nick Crast <nrcrast@gmail.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
The gpio pins numbers aren't just matching the physical pin numbers...
on some distros like raspbian, with a kernel explicitly setting the
base to 0, it works, but for kernels using the first free slot it
doesn't (see gpiochip_find_base() in kernel's gpiolib.c).
To get the proper gpio pin value, we thus need to find the base for
the corresponding gpiochip. For the raspberry pi, we search for the
chip with a label containing 'bcm2835'.
Signed-off-by: Cédric Bosdonnat <cbosdonnat@suse.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
While some distributions have a modified /proc/cpuinfo including
the board revision for raspberry pi, most distributions don't
have this.
In order to guess the raspberry pi version in such cases, use
the /proc/device-tree/compatible content as a fallback solution.
The values expected from this file have been taken from
upstream kernel documentation:
Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
Signed-off-by: Cédric Bosdonnat <cbosdonnat@suse.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
As per Documentation/ABI/testing/sysfs-firmware-ofw, perfer
/proc/device-tree over /sys/firmware/devicetree/base as this
is the stable one.
Signed-off-by: Cédric Bosdonnat <cbosdonnat@suse.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
Change PLATFORM_RASPBERRY_PI_ZERO into an integer to avoid
build error when comparing it to integer platform_detected.
Signed-off-by: Cédric Bosdonnat <cbosdonnat@suse.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
Like the beaglebone, the phyBOARD-Wega also got an am335x.
So I merged the four mmap-functions for gpio_context and some
identical defines in a separate header and c-file.
The new platform support-files are based on beaglebone-files.
The documentation of phyBOARD-Wega is still in process,
but for now there are enough informations.
At this time it is possible to use GPIO-Pins and Uart0
(tested via python with mraa). The code for using SPI, I2C and
PWM is also still in process and not tested yet.
Signed-off-by: Norbert Wesp <nwesp@phytec.de>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
Every 96Boards baseboard uses the same expansion connector, but the
current 96Boards initialization code assigns the SoC specific GPIO
numbers instead of being consistent across all boards. Change the code
to assign 96Boards GPIO-A through GPIO-L to MRAA GPIOs 23-34.
v2: Create info for all the LS connector pins, not just the GPIO pins.
This gives us room to describe other pins in the future.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Somewhere between kernel v3.18 and v4.4 the output of /proc/cpuinfo
stopped showing the board model. This confused MRAA when running on
HiKey. Eventually we want to do a better job of getting the kernel to
express hardware information to userspace, but in the mean time fix the
test so that MRAA will work on HiKey.
Signed-off-by: Grant Likely <grant.likely@linaro.org>
Cc: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Brendan Le Foll <brendan.le.foll@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
Switch to using calloc on all calls to malloc where the memory isn't
initialized. For things like the mraa_board_t, not allocating all to zero
causes issues such as with the sub_platform member, where if that's not zero
mraa_get_platform_type will try to dereference a random memory location for the
sub_platform->platform_name, which can result in segmentation faults and other
issues.
Note that in some places where immediately after the malloc call is a copy
operation, there is no need for calloc, as all the memory gets overwritten
anyways, but in cases where there may or may not be memory written to (such as
in mraa_file_contains, with reading from a file), even though in most cases the
memory is overwritten, it could be the case that the read operation does
nothing, but the memory still has non-zero values, by virtue of the fact it
wasn't overwritten.
Signed-off-by: Ian Johnson <ijohnson@wolfram.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
