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118 Commits

Author SHA1 Message Date
Alex Tereschenko
32196d10e9 joule: align SPI bus numbering with reality
Also update docs to make the numbering and pins used crystal clear.

Closes #758.

Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
2017-06-15 20:49:18 +02:00
Alex Tereschenko
722b83b95c intel_edison_fab_c.c: fix unused variables
Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2017-05-29 18:47:45 +02:00
Alex Tereschenko
0654183b9a stability: replace sprintf with snprintf to avoid potential overflows
Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
2017-05-15 21:04:18 +02:00
Brendan Le Foll
a0332b14b5 Revert "x86.c: add NUC5i7RYB to the list of known NUC5 platforms"
This reverts commit 2f51627d18.

Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2017-05-12 01:23:58 -07:00
Nicola Lunghi
def0a6aed1 up.c: Fixed pin name size on up board
Signed-off-by: Nicola Lunghi <nicola.lunghi@emutex.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2017-05-12 01:23:47 -07:00
Mihai Tudor Panu
2f51627d18 x86.c: add NUC5i7RYB to the list of known NUC5 platforms
While the NUC5i7RYB doesn't provide any built-in IO, this change will at least allow it to be used with a subplatform from IDEs that filter out unknown devices (e.g. Intel XDK).

Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
2017-04-19 15:31:07 -07:00
Nicola Lunghi
a3f5db1d84 up.c: Removed dead code in up.c
Signed-off-by: Nicola Lunghi <nicola.lunghi@emutex.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2017-04-02 19:59:53 +02:00
Arun Ravindran
5e34a5cd3b intel_joule: Update doc with correct PIN behavior
GPIO and I2C functions of some PINs are not possible
with default BIOS configuration. Current documentation
wrongly shows that the PINs can work as both GPIO and I2C.

This patch fixes this issue and also updated pin conf for
I2C 1 and 2 to disable GPIO functionality.

Signed-off-by: Arun Ravindran <arun.ravindran@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2017-03-20 16:44:18 +00:00
Arun Ravindran
dd19634889 joule: Fixing descripencies in gpio numbers
The earlier patches did not fix the following issues.

1) gpio number used for ISH I2C 0 and I2C 1 were not correct
2) gpio number used in ISH I2C 1 and I2C 2 were not correct
3) ISH UART 0 gpio numbers were wrong

This patch fixes this issue and also update the doc.

Signed-off-by: Arun Ravindran <arun.ravindran@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2017-03-20 08:37:24 +00:00
Arun Ravindran
1c4b1fc329 joule: Fix issue with ISH UART name
MRAA is using gpio 484, 483, 485 and 486 as ISH UART1.
But J13 expansion connector doesn't expose ISH UART1,
instead it exposes ISH UART0 as per dev kit hardware guide.

This patch fixes this descrpency and renames the UART and
also enables the GPIO usage.

Signed-off-by: Arun Ravindran <arun.ravindran@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2017-03-13 22:11:40 +01:00
Arun Ravindran
c7a4a6db34 intel_joule_expansion.c: Fix issue with gpio-339 mapping
The mapping for gpio-339 went away with commit

gpio-339 is available as LED102 or ISH_IO2

Signed-off-by: Arun Ravindran <arun.ravindran@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2017-03-13 21:54:27 +01:00
Arun Ravindran
0470aebee6 joule: Fix issues with gpio mapping
The GPIOs are not mapped correctly in MRAA for tuchuk board.

This patch corrects the GPIO maps and the PIN assignments.

Note:
1) There are nothing called I2S(x)SDO and I2S(x)SDI available over breakout
   pins, the usage is commented now.
2) There is nothing called SPP0FS3, is now commented, what we have is SPP1FS3.
3) I2C1SDA available twise 15 and 71. PIN 71 as per gpio used should be renamed as ISHI2C0SDA
4) I2C1SCL available twise 17 and 73. PIN 73 as per gpio used should be renamed as ISHI2C0SCL
5) UART1TX available twise 22 and 74. PIN 74 as per gpio used is ISHUART1TXD
   and is not available in breakout.
6) UART1RX available twise 24 and 76. PIN 76 as per gpio used is ISHUART1RXD
   and is not available in breakout.
7) I2C2SDA available twise 19 and 75. PIN 75 as per gpio used is ISHI2C1SDA
   and is not available in breakout pins
8) I2C2SCL available twise 21 and 77. PIN 75 as per gpio used is ISHI2C1SCL
   and is not available in breakout pins
9) PIN 78 UART1RT as per GPIO used is ISHUART1RT and is not available in breakout pins
10) PIN 80 UART1CT as per GPIO is ISHUART1CT and is not available in breakout pins

BIOS used is 193

Signed-off-by: Arun Ravindran <arun.ravindran@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2017-03-09 17:25:07 +01:00
Wai Lun
0092e13f57 Joule: Update references to the Intel Joule
GT/GrosseTete -> Joule. This commit deprecates the MRAA_INTEL_GT_TUCHUCK
mraa_platform_t value and links the grossetete.md page to joule.md.

Signed-off-by: Wai Lun Poon <wai.lun.poon@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2017-02-27 18:06:40 +01:00
Nicola Lunghi
6fabccf131 x86: Normalized function names in up & byt platform
Signed-off-by: Nicola Lunghi Emutex <nicola.lunghi@emutex.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2017-02-06 21:32:54 +00:00
Mihai Tudor Panu
72261d61bd joule: enable ISH_GPIOs and GPIO_22 exposed on J12 header
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2017-01-24 19:43:19 +01:00
Alex Tereschenko
af051d820a intel_edison_fab_c.c: further fix for PWM disable problem
This adds logic to save PWM duty when disabling the pin (which sets
the duty to 0), and restore it when re-enabling the pin.

Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-12-29 18:48:53 +00:00
belugon
2558866d4a intel_edison_fab_c.c: Fix edison disabled pwm stuck at high
Edison pwm can stuck at high if pin is disabled during ON pwm peroid.
Workaround is to force zero duty time before disabling the pin.

Signed-off-by: Billy Bai <belugon@outlook.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-12-29 18:48:41 +00:00
Brendan Le Foll
c1017bb6ea intel_gt_tuchuck.c: Clear uart pin cap since bios doesn't allow muxing
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-11-30 11:37:47 +01:00
Dan O'Donovan
d2f1b068b7 update UP board hardware details and enable ADC
Some details regarding the UP board are not in-sync with the
final production version of the board.  This update adds an
ADC, removes a UART, and some corrections in the docs for UP.

Signed-off-by: Dan O'Donovan <dan@emutex.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-11-21 10:24:05 +00:00
Brendan Le Foll
4a33aca8fd intel_gt_tuchuck.c: Use new mraa_find_i2c_bus_pci to find i2c busses
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-11-02 15:30:56 +00:00
Brendan Le Foll
cada819c39 intel_edison_fab_c.c: don't undo muxing if we don't own the pin
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-10-26 14:24:50 +01:00
SaschaWeisenberger
be22844922 src/x86/x86.c: add support for Siemens SIMATIC IOT2000
The Siemens device "SIMATIC IOT2000" is identical to the Intel Galileo
Gen 2 regarding the gpios. So if the board name is "SIMATIC IOT2000"
treat the board as if it is Galileo Gen 2.

Signed-off-by: Sascha Weisenberger sascha.weisenberger@siemens.com
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-09-27 13:08:44 +01:00
Brendan Le Foll
6c85b61daa mraa: Fix compiler warnings unused vars and useless statements
Should have 0 functionality effect, just cleans up a few things. Fixes #577

Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-09-13 11:20:41 +01:00
Brendan Le Foll
ff3b3004da intel_gt_tuchuck.c: Add SPI to joule pinmap file
This commit fixes documentation for SPI bus to match latest changes in pinmap
file

Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-09-07 13:51:32 +01:00
Brendan Le Foll
8ec4fcb333 intel_galileo_rev_g.c: use pincmd to set OUT_HIGH instead of value
The i/o expander looses connection as soon as direction is set so use direction
OUT_HIGH instead of setting value after direction. Closes #573

Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-09-02 12:00:29 +01:00
Brendan Le Foll
94b7477212 intel_gt_tuchuck.c: Make sure GPIOs are set to 0 muxes
Use calloc for pinsize and set mux_total to 0 in all gpios

Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-08-30 12:26:36 +01:00
Brendan Le Foll
1589389c3f intel_gt_tuchuck.c: LED101 reset to GPIO338
A bios change to 395 was never made so this broke LED101

Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-08-30 11:40:32 +01:00
Thomas Ingleby
fce4daab02 mraa: Correct spelling of capabilities
Type was correctly spelt, but the member in the platform strut was not.
My mistake from 2014.

Signed-off-by: Thomas Ingleby <thomas.ingleby@intel.com>
2016-08-08 21:44:00 +02:00
Brendan Le Foll
36153ad7ad intel_galileo_rev_d.c: Move code for gen1 from pwm.c to advance function
This re-enables correct PWM on gen1

Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-08-03 13:27:35 +01:00
Brendan Le Foll
874d0f47bd gt: allow for i2c bus to move around a little
Unfortunately GT has alot of i2c buses, the second lot of designware buses can
turn up after the i915 i2c buses but since they all have the same name, we do a
dumb check to see if they are 5/6 or 9/10. Hopefully future kernel/firmware
will let us do something smarter.

Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-07-12 12:26:46 +01:00
Mihai Tudor Panu
eabee5f864 gt-tuchuck: fix I2C bus typos in board definition file
Signed-off-by: Mihai Tudor Panu <mihai.tudor.panu@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-07-09 08:40:10 +01:00
Bruce Beare
c1fd2896c2 edison: fix edison spelling errors
Signed-off-by: Bruce Beare <bruce.j.beare@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-06-29 09:59:29 +01:00
Bruce Beare
5704c15665 gt: Add module lights to the gpio HAL
Signed-off-by: Bruce Beare <bruce.j.beare@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-06-29 09:58:57 +01:00
Alex Tereschenko
f9bc314223 x86.c: fixed typo in Tuchuck board forced enablement
Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-06-27 11:43:38 +01:00
Brendan Le Foll
0577321f4c intel_gt: add support for gt + Tuchuck board
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-06-23 16:16:38 +01:00
Alex Tereschenko
8af6843566 PWM: added workaround for Edison's problem with 0% duty
As described in issue #91, on Edison setting 0% duty doesn't
disable the PWM on a pin completely.

Therefore we add a couple of Edison-specific _pre functions
and an internal PWM state variable, which we use to toggle PWM
enabled/disabled based on what duty is set for the pin.

Closes #91.

Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-06-16 14:12:33 +01:00
Houman brinjcargorabi
8329bcab62 intel_edison_fab_c.c: fixed the pins not being freed in the event of a tristate read failing
Signed-off-by: Houman Brinjcargorabi <houman.brinjcargorabi@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-06-01 11:29:17 +01:00
Houman brinjcargorabi
e8d6f38ee0 intel_nuc5.c: Fixed incorrect I2C numbering, effectively not shifting the pin number correctly
Signed-off-by: Houman Brinjcargorabi <houman.brinjcargorabi@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-06-01 11:29:15 +01:00
Houman brinjcargorabi
a9de84b74a intel_galileo_rev_g.c: Corrected typo in mapping re setting the pincmd for GPIO2
Fixes typo in 95c259f6b2

Acked-by: Houman Brinjcargorabi <houman.brinjcargorabi@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-05-20 11:26:59 +01:00
Brendan Le Foll
022b36355f x86: Fix capabilities being initialised with only 7 bits
This whilst ugly should not cause an issue because of our use of calloc.

Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-05-19 10:23:10 +01:00
Eugene Bolshakov
6d8ec87e0e edison: change pin initialization by adding pin commands
Pullup/pulldown resistors are disabled during GPIO initialization.

Signed-off-by: Eugene Bolshakov <pub@relvarsoft.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-04-19 18:39:11 +01:00
Brendan Le Foll
296ed38227 up.c: Remove warnings about unsigned ints being passed
Whilst not the cleanest and the headers could do with an update, this is a
short term solution to stop the warnings

Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-03-24 09:36:05 +00:00
Eugene Bolshakov
3397c95c0a intel_galileo_rev_d.c: Add pin commands
Signed-off-by: Eugene Bolshakov <pub@relvarsoft.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-03-22 18:12:29 +00:00
Eugene Bolshakov
95c259f6b2 mraa.c: change pin initialization and fix Galileo Gen2 AIO
Add pin commands. Old mraa_setup_mux_mapped style is used for other boards
(pincmd = PINCMD_UNDEFINED) where pincmds are not defined.Remove useless
pullup_enable code, Galileo Gen2: review all pin mux and add commands Galileo
Gen2: remove doubled functionality: mraa_intel_galileo_gen2_i2c_init_pre and
mraa_intel_galileo_gen2_uart_init_pre. Galileo Gen2: fix "Invalid AIO pin
specified - do you have an ADC?" error. Galileo Gen2: pullup/pulldown
resistors are disabled during UART/GPIO/SPI/I2C/UIO initialization. Use
mraa_gpio_mode to enable resistors.

Signed-off-by: Eugene Bolshakov <pub@relvarsoft.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-03-22 18:12:29 +00:00
Dan O'Donovan
2b73083955 up: adding option to build for UP platform only
Adding cmake option to build for UP platform only:
 -DMRAAPLATFORMFORCE=MRAA_UP

Signed-off-by: Dan O'Donovan <dan@emutex.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-02-24 15:10:20 +00:00
Dan O'Donovan
f9501c5c78 up: add support for UP Board
Add support for UP board (www.up-board.org), scoping
the following functions available via 40-pin header:
* GPIO (via sysfs)
* UART
* I2C
* SPI
* PWM

Validated on UP board v0.2, running ubilinux 3.0

Signed-off-by: Dan O'Donovan <dan@emutex.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-02-24 15:10:20 +00:00
Brendan Le Foll
ca11078fd0 intel_edison_fab_c.c: spi_init_pre on arduino should be called on mraa_init()
It's required to make ADC work as well as the SPI bus

Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-02-20 09:24:09 +00:00
Alex Tereschenko
baa1fcf7be intel_edison_fab_c.c: Fixed file descriptor leak in case of read error
Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-02-16 17:13:09 +00:00
Alex Tereschenko
b33bd5ccd2 intel_edison_fab_c.c: Enhanced detection of Arduino expansion board
Closes #318.

Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-02-12 11:29:04 +00:00
Constantin Musca
9202eb172d intel_edison_fab_c: don't call mraa_intel_edison_misc_spi for miniboard
mraa_intel_edison_misc_spi is specific to the Arduino board.
Call it only when miniboard is not 1.

Signed-off-by: Constantin Musca <constantin.musca@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
2016-02-08 10:03:17 +00:00