This commit cleans up the 96boards board support by sorting the boards
in alphabetical manner and also executing clang-format for 96boards.c
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Add support for Hikey960 board from HiSilicon based on their Kirin960 SoC.
Peripherals supported:
1. GPIO
2. UART
3. I2C
For GPIO only Chardev interface has been added since this board only supports
>=4.15 kernel and using legacy sysfs interface is highly discouraged.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: malikabhi05 <abhishek.malik@intel.com>
According to SonarCloud's email notification,
they're dropping sonarqube.com in favor of sonarcloud.io.
Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
fixes naming in up and up2 platform
- changed the name of the i2c function
- add a warning in the log if a name is not found
Signed-off-by: Nicola Lunghi <nicola.lunghi@emutex.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
This commit adds a MRAA platform for the UP Squared board, EVT3 revision.
It handles the relevant FPGA configuration updates when using MRAA to
change pin modes or toggle GPIO directions.
Signed-off-by: Javier Arteaga <javier@emutex.com>
Signed-off-by: Nicola Lunghi <nicola.lunghi@emutex.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
* Use docker images from docker hub instead of building them on Travis
* Fix doxygen warnings for C/C++ Documentation
* Fix examples inclusion in documentation
* Modify Travis build matrix to include stages and additional jobs
* Update doxygen2jsdoc submodule
* Add doxyport submodule
* Generate documentation for each language in Travis
* Add sonar.java.binaries to sonar-scan.sh
Signed-off-by: Nicolas Oliver <dario.n.oliver@intel.com>
MinnowMax is obsoleted, replaced with the Minnow Turbot - updated the web links
to point to the legacy board pages, and the new board where appropriate. Pin
26 - Added a pin function for the I2S MCLK
There is more work to do to capture and document all the changes.
Signed-off-by: |\/|ark van der Pol <markx.van.der.pol@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
First submission for 96Boards markdown in docs folder. Currently
hosts information and resources for three Consumer Edition
96Boards including DragonBoard 410c, HiKey, and Bubblegum-96.
Plans to expand on this doc as more boards are enabled. Will also
highlight any notes as things come up.
Signed-off-by: Robert Wolff <robert.wolff@linaro.org>
* Update documentation for C methods
* Update documentation for CXX methods
* Update build instructions for building on AT Peripheral Manager Client
Signed-off-by: Noel Eck <noel.eck@intel.com>
GPIO and I2C functions of some PINs are not possible
with default BIOS configuration. Current documentation
wrongly shows that the PINs can work as both GPIO and I2C.
This patch fixes this issue and also updated pin conf for
I2C 1 and 2 to disable GPIO functionality.
Signed-off-by: Arun Ravindran <arun.ravindran@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
The earlier patches did not fix the following issues.
1) gpio number used for ISH I2C 0 and I2C 1 were not correct
2) gpio number used in ISH I2C 1 and I2C 2 were not correct
3) ISH UART 0 gpio numbers were wrong
This patch fixes this issue and also update the doc.
Signed-off-by: Arun Ravindran <arun.ravindran@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
MRAA is using gpio 484, 483, 485 and 486 as ISH UART1.
But J13 expansion connector doesn't expose ISH UART1,
instead it exposes ISH UART0 as per dev kit hardware guide.
This patch fixes this descrpency and renames the UART and
also enables the GPIO usage.
Signed-off-by: Arun Ravindran <arun.ravindran@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
The GPIOs are not mapped correctly in MRAA for tuchuk board.
This patch corrects the GPIO maps and the PIN assignments.
Note:
1) There are nothing called I2S(x)SDO and I2S(x)SDI available over breakout
pins, the usage is commented now.
2) There is nothing called SPP0FS3, is now commented, what we have is SPP1FS3.
3) I2C1SDA available twise 15 and 71. PIN 71 as per gpio used should be renamed as ISHI2C0SDA
4) I2C1SCL available twise 17 and 73. PIN 73 as per gpio used should be renamed as ISHI2C0SCL
5) UART1TX available twise 22 and 74. PIN 74 as per gpio used is ISHUART1TXD
and is not available in breakout.
6) UART1RX available twise 24 and 76. PIN 76 as per gpio used is ISHUART1RXD
and is not available in breakout.
7) I2C2SDA available twise 19 and 75. PIN 75 as per gpio used is ISHI2C1SDA
and is not available in breakout pins
8) I2C2SCL available twise 21 and 77. PIN 75 as per gpio used is ISHI2C1SCL
and is not available in breakout pins
9) PIN 78 UART1RT as per GPIO used is ISHUART1RT and is not available in breakout pins
10) PIN 80 UART1CT as per GPIO is ISHUART1CT and is not available in breakout pins
BIOS used is 193
Signed-off-by: Arun Ravindran <arun.ravindran@intel.com>
Signed-off-by: Brendan Le Foll <brendan.le.foll@intel.com>
